Advances in excimer laser technology for sub-0.25-μm lithography. - Palash Das; Richard L. Sandstrom (Proc. IEEE, 2002)

Signature analysis for synthesis of reversible circuit. - Palash Das; Bikromadittya Mondal (VDAT, 2014)

A comprehensive fault diagnosis technique for reversible logic circuits. - Bikromadittya Mondal; Palash Das; Pradyut Sarkar; Susanta Chakraborty (Comput. Electr. Eng., 2014)

Towards Near-Data Processing of Compare Operations in 3D-Stacked Memory. - Palash Das; Hemangee K. Kapoor (ACM Great Lakes Symposium on VLSI, 2018)

Towards Near Data Processing of Convolutional Neural Networks. - Palash Das; Shivam Lakhotia; Prabodh Shetty; Hemangee K. Kapoor (VLSID, 2018)

Dimming Hybrid Caches to Assist in Temperature Control of Chip MultiProcessors. - Chirag Joshi; Palash Das; Ashwini A. Kulkarni; Hemangee K. Kapoor (ACM Great Lakes Symposium on VLSI, 2020)

CLU: A Near-Memory Accelerator Exploiting the Parallelism in Convolutional Neural Networks. - Palash Das; Hemangee K. Kapoor (ACM J. Emerg. Technol. Comput. Syst., 2021)

nZESPA: A Near-3D-Memory Zero Skipping Parallel Accelerator for CNNs. - Palash Das; Hemangee K. Kapoor (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Hydra: A near hybrid memory accelerator for CNN inference. - Palash Das; Ajay Joshi; Hemangee K. Kapoor (DATE, 2022)

ZaLoBI: Zero avoiding Load Balanced Inference accelerator. - Imlijungla Longchar; Palash Das; Hemangee K. Kapoor (VLSI-SoC, 2022)

NDIE: A Near DRAM Inference Engine Exploiting DIMM's Parallelism. - Palash Das; Hemangee K. Kapoor (APCCAS, 2023)

ALAMNI: Adaptive LookAside Memory Based Near-Memory Inference Engine for Eliminating Multiplications in Real-Time. - Palash Das; Shashank Sharma; Hemangee K. Kapoor (IEEE Trans. Computers, 2023)

edAttack: Hardware Trojan Attack on On-Chip Packet Compression. - Atul Kumar; Dipika Deb; Shirshendu Das; Palash Das (IEEE Des. Test, 2023)

Hybrid Token Selector based Accelerator for ViTs. - Akshansh Yadav; Anadi Goyal; Palash Das (DATE, 2025)

Programmable Optically Variable Resistors: Automating the Design and Measurement of Transistor Biasing Circuits. - Sneha Ray; Aritra Acharyya; Angsuman Sarkar; Palash Das; R. Das; T. Halder; A. Maji; S. B. R. Chowdhury; S. R. Hossain; A. Gain; S. S. Mondal; S. Mondal; et al. (J. Circuits Syst. Comput., 2025)