A high speed, memory efficient line based VLSI architecture for the dual mode inverse discrete wavelet transform of JPEG2000 decoder. - Pallab Kumar Nath; Swapna Banerjee (Microprocess. Microsystems, 2016)

FPGA based Compressive Sensing Framework for Video Compression on Edge Devices. - Abin Bassam Ayub; Pallab Kumar Nath; Venkat Rangan; Chetan Singh Thakur (VDAT, 2020)

A high throughput pass parallel block decoder architecture for JPEG 2000 that prevents stalling in the decoding process. - Pallab Kumar Nath; Swapna Banerjee (Integr., 2020)

High throughput unified architecture of LEA algorithm for image encryption. - Zeesha Mishra; Pallab Kumar Nath; Bibhudendra Acharya (Microprocess. Microsystems, 2020)

Smartphone-Based Point-of-Care System Using Continuous-Wave Portable Doppler. - Biswabandhu Jana; Rakesh Biswas; Pallab Kumar Nath; Goutam Saha 001; Swapna Banerjee (IEEE Trans. Instrum. Meas., 2020)

Corrigendum to High throughput unified architecture of LEA algorithm for image encryption' Microprocessors and Microsystems Vol 78 (2020) 1-10 - Zeesha Mishra; Pallab Kumar Nath; Bibhudendra Acharya (Microprocess. Microsystems, 2021)

A Single-Chip Solution for Diagnosing Peripheral Arterial Disease. - Biswabandhu Jana; Pallab Kumar Nath (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Multiplierless MP-Kernel Machine for Energy-Efficient Edge Devices. - Abhishek Ramdas Nair; Pallab Kumar Nath; Shantanu Chakrabartty; Chetan Singh Thakur (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Multiplierless In-filter Computing for tinyML Platforms. - Abhishek Ramdas Nair; Pallab Kumar Nath; Shantanu Chakrabartty; Chetan Singh Thakur (VLSID, 2024)

Neuromorphic Retina: An FPGA-based Emulator. - Prince Phillip; Pallab Kumar Nath; Kapil Jainwal; André van Schaik; Chetan Singh Thakur (CoRR, 2025)