Application specific processor vs. microblaze soft core RISC processor: FPGA based performance and CPR analysis. - Pallabi Sarkar; Reza Sedaghat; Anirban Sengupta (ACAI, 2011)

Integrated design space exploration based on power-performance trade-off using genetic algorithm. - Anirban Sengupta; Reza Sedaghat; Pallabi Sarkar (ACAI, 2011)

Integrated scheduling, allocation and binding in High Level Synthesis for performance-area tradeoff of digital media applications. - Anirban Sengupta; Reza Sedaghat; Pallabi Sarkar; Summit Sehgal (CCECE, 2011)

Priority function based power efficient rapid Design Space Exploration of scheduling and module selection in high level synthesis. - Anirban Sengupta; Reza Sedaghat; Pallabi Sarkar; Summit Sehgal (CCECE, 2011)

Rapid exploration of integrated scheduling and module selection in high level synthesis for application specific processor design. - Anirban Sengupta; Reza Sedaghat; Pallabi Sarkar (Microprocess. Microsystems, 2012)

A multi structure genetic algorithm for integrated design space exploration of scheduling and allocation in high level synthesis for DSP kernels. - Anirban Sengupta; Reza Sedaghat; Pallabi Sarkar (Swarm Evol. Comput., 2012)

A multi parametric optimization based novel approach for an efficient design space exploration for ASIC design. - Tulasi Krishna; Priyam Sachdeva; Suraj Kumar Dhanuka; Mohit Gagrani; Pallabi Sarkar (ICACCI, 2013)

GA driven integrated exploration of loop unrolling factor and datapath for optimal scheduling of CDFGs during high level synthesis. - Pallabi Sarkar; Anirban Sengupta; Mrinal Kanti Naskar (CCECE, 2015)

A Firefly Algorithm Driven Approach for High Level Synthesis. - Pallabi Sarkar; Anirban Sengupta; Santosh Rathlavat; Mrinal Kanti Naskar (iNIS, 2017)

Designing Low-Cost Hardware Accelerators for CE Devices [Hardware Matters]. - Pallabi Sarkar; Anirban Sengupta; Santosh Rathlavat; Mrinal Kanti Naskar (IEEE Consumer Electron. Mag., 2017)

Obfuscation of Fault Secured DSP Design Through Hybrid Transformation. - Anirban Sengupta; Shubha Neema; Pallabi Sarkar; Sri Harsha P; Saraju P. Mohanty; Mrinal Kanti Naskar (ISVLSI, 2018)

Optimizing DSP Cores Using Design Transformation [Hardware Matters]. - Dipanjan Roy; Pallabi Sarkar; Anirban Sengupta; Mrinal Kanti Naskar (IEEE Consumer Electron. Mag., 2018)

Signature-Free Watermark for Protecting Digital Signal Processing Cores Used in CE Devices [Hardware Matters]. - Pallabi Sarkar; Dipanjan Roy; Anirban Sengupta; Mrinal Kanti Naskar (IEEE Consumer Electron. Mag., 2019)

Securing IP Cores in CE Systems using Key-driven Hash-chaining based Steganography. - Mahendra Rathor; Pallabi Sarkar; Vipul Kumar Mishra; Anirban Sengupta (ICCE-Berlin, 2020)

System Complexity Reduction Using 3-D Matrices and Novel Logic Gates. - Nameshwari Verma; Pallabi Sarkar (ICCCNT, 2023)