A High-level Interconnect Power Model for Design Space Exploration. - Pallav Gupta; Lin Zhong 001; Niraj K. Jha (ICCAD, 2003)

An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology. - Pallav Gupta; Niraj K. Jha (DATE, 2004)

Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies. - Rui Zhang; Pallav Gupta; Lin Zhong 001; Niraj K. Jha (DATE, 2004)

An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks. - Pallav Gupta; Rui Zhang; Niraj K. Jha (ICCD, 2004)

Efficient fingerprint-based user authentication for embedded systems. - Pallav Gupta; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (DAC, 2005)

Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies. - Rui Zhang; Pallav Gupta; Niraj K. Jha (VLSI Design, 2005)

Threshold network synthesis and optimization and its application to nanotechnologies. - Rui Zhang; Pallav Gupta; Lin Zhong 001; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Test generation for combinational quantum cellular automata (QCA) circuits. - Pallav Gupta; Niraj K. Jha; Loganathan Lingappan (DATE, 2006)

An Algorithm for Synthesis of Reversible Logic Circuits. - Pallav Gupta; Abhinav Agrawal 002; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies. - Rui Zhang; Pallav Gupta; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

A Test Generation Framework for Quantum Cellular Automata Circuits. - Pallav Gupta; Niraj K. Jha; Loganathan Lingappan (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Automatic Test Generation for Combinational Threshold Logic Networks. - Pallav Gupta; Rui Zhang; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip. - Naghmeh Karimi; Zhiqiu Kong; Krishnendu Chakrabarty; Pallav Gupta; Srinivas Patil (Asian Test Symposium, 2011)

Case study: Alleviating hotspots and improving chip reliability via carbon nanotube thermal interface. - Wei Zhang 012; Jiale Huang; Shengqi Yang; Pallav Gupta (DATE, 2011)

Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs. - Xiaofang (Maggie) Wang; Pallav Gupta (ACM Trans. Design Autom. Electr. Syst., 2011)

Test generation for clock-domain crossing faults in integrated circuits. - Naghmeh Karimi; Krishnendu Chakrabarty; Pallav Gupta; Srinivas Patil (DATE, 2012)

A physical design tool for carbon nanotube field-effect transistor circuits. - Jiale Huang; Minhao Zhu; Shengqi Yang; Pallav Gupta; Wei Zhang 012; Steven M. Rubin; Gilda Garretón; Jin He 003 (ACM J. Emerg. Technol. Comput. Syst., 2012)

Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling. - Shengqi Yang; Pallav Gupta; Marilyn Wolf; Dimitrios N. Serpanos; Vijaykrishnan Narayanan; Yuan Xie 001 (ACM Trans. Embed. Comput. Syst., 2012)

NBTI-aware circuit node criticality computation. - Shengqi Yang; Wenping Wang 004; Mark Hagan; Wei Zhang 012; Pallav Gupta; Yu Cao 001 (ACM J. Emerg. Technol. Comput. Syst., 2013)

Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal Structure. - Hao Liang 003; Wei Zhang 012; Jiale Huang; Shengqi Yang; Pallav Gupta (IEEE Trans. Very Large Scale Integr. Syst., 2015)

An Effective Methodology for Automated Diagnosis of Functional Pattern Failures to Support Silicon Debug. - Pallav Gupta (ITC, 2018)

Online Scan Diagnosis : A Novel Approach to Volume Diagnosis. - I-De Huang; Pallav Gupta; Loganathan Lingappan; Vijay Gangaram (ITC, 2018)

Empowering healthcare with BIEH - blockchain inter-operable electronic health record scheme. - Pallav Gupta; Swarab Raul; S. Shoba; Karthika Veeramani (Clust. Comput., 2025)