Circuit Optimization at 22nm Technology Node. - Angada B. Sachid; Pallavi Paliwal; S. Joshi; Maryam Shojaei Baghini; Dinesh Sharma; V. Ramgopal Rao (VLSI Design, 2012)

Tradeoffs between settling time and jitter in phase locked loops. - Pallavi Paliwal; Priyank Laad; Mohanrao Sattineni; Shalabh Gupta (MWSCAS, 2013)

High resolution digital-to-time converter for low jitter digital PLLs. - Anil Chawda; Pallavi Paliwal; Priyank Laad; Shalabh Gupta (ICECS, 2014)

A low-jitter digital-to-time converter with look-ahead multi-phase DDS. - Harishankar Sahu; Pallavi Paliwal; Vivek Yadav; Shalabh Gupta (LASCAS, 2016)

A Fast Settling 4.7-5 GHz Fractional-N Digital Phase Locked Loop. - Pallavi Paliwal; Jaydip Fadadu; Anil Chawda; Shalabh Gupta (VLSID, 2016)

Stability Analysis for Fast Settling Switched DPLL. - Pallavi Paliwal; Debasattam Pal; Shalabh Gupta (CoRR, 2018)

A High-Resolution Digital Phase Interpolator Based CDR with a Half-Rate Hybrid Phase Detector. - Arun Goyal; Souvik Ghosh; Sandeep Goyal; Pallavi Paliwal; Shalabh Gupta (ISCAS, 2019)

A Fast Settling Fractional-N DPLL With Loop-Order Switching. - Pallavi Paliwal; Vivek Yadav; Zeeshan Ali; Shalabh Gupta (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A Fast Locking Ring Oscillator Based Fractional-N DPLL With an Assistance From a LUT-Based FSM. - Zeeshan Ali; Pallavi Paliwal; Rupesh Lad; Dhanraj Bhukya; Shalabh Gupta (ISCAS, 2022)

Stability Analysis for Fast Settling Switched Digital Phase-Locked Loops (DPLLs). - Zeeshan Ali; Pallavi Paliwal; Phani Raj; Deepak Anand; Debasattam Pal; Shalabh Gupta (IEEE Control. Syst. Lett., 2023)