Pass Transistor Operation Modeling for Nanoscale Technologies. - Panagiotis Chaourani; Ilias Pappas 001; Spiros Nikolaidis 001; Abdoul Rjoub (PATMOS, 2011)

A unified CMOS inverter model for planar and FinFET nanoscale technologies. - Panagiotis Chaourani; Spyridon Nikolaidis 001 (DDECS, 2014)

An analytical model for the CMOS inverter. - Panagiotis Chaourani; Ioannis Messaris; Nikolaos Fasarakis; Maria Ntogramatzi; Sotirios K. Goudos; Spiros Nikolaidis 001 (PATMOS, 2014)

A study for replacing CMOS gates by equivalent inverters. - Christina Galani; Andreas Tsormpatzoglou; Panagiotis Chaourani; Ioannis Messaris; Spiros Nikolaidis 001 (ISCAS, 2015)

Enabling area efficient RF ICs through monolithic 3D integration. - Panagiotis Chaourani; Per-Erik Hellström; Saul Rodriguez 001; Raul Onet; Ana Rusu (DATE, 2017)

An Evaluation of the Equivalent Inverter Modeling Approach. - Ioannis Messaris; Christina Galani; Maria Ntogramatzi; Nikolaos Karagiorgos; Panagiotis Chaourani; Andreas Tzormpatzoglou; Sotirios K. Goudos; Spyridon Nikolaidis 001 (Circuits Syst. Signal Process., 2018)

Regional Clock Tree Generation by Abutment in Synchoros VLSI Design. - Dimitrios Stathis 001; Panagiotis Chaourani; Syed M. A. H. Jafri; Ahmed Hemani (CoRR, 2019)

Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines. - Panagiotis Chaourani; Saul Rodriguez 001; Per-Erik Hellström; Ana Rusu (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Sequential 3D Integration - Design Methodologies and Circuit Techniques. - Panagiotis Chaourani (2019)

Clock tree generation by abutment in synchoros VLSI design. - Dimitrios Stathis 001; Panagiotis Chaourani; Syed M. A. H. Jafri; Ahmed Hemani (Microprocess. Microsystems, 2023)