FPGA based implementation of decoder for array low-density parity-check codes. - Pankaj Bhagawat; Momin Uppal; Gwan Choi (ICASSP (5), 2005)

A High-Speed Fully-Programmable VLSI Decoder for Regular LDPC Codes. - Euncheol Kim; Nikhil Jayakumar; Pankaj Bhagawat; Anand Selvarathinam; Gwan Choi; Sunil P. Khatri (ICASSP (3), 2006)

An FPGA Implementation of Dirty Paper Precoder. - Pankaj Bhagawat; Weihuang Wang; Momin Uppal; Gwan Choi; Zixiang Xiong; Mark B. Yeary; Alan Harris (ICC, 2007)

High performance on the fly reconfigurable MIMO detector. - Pankaj Bhagawat; Rajballav Dash; Gwan Choi (ACSCC, 2008)

Dynamically reconfigurable soft output MIMO detector. - Pankaj Bhagawat; Rajballav Dash; Gwan Choi (ICCD, 2008)

Architecture for reconfigurable MIMO detector and its FPGA implementation. - Pankaj Bhagawat; Rajballav Dash; Gwan Choi (ICECS, 2008)

Array like runtime reconfigurable MIMO detectors for 802.11n WLAN: a design case study. - Pankaj Bhagawat; Rajballav Dash; Gwan S. Choi (ASP-DAC, 2009)

Systolic like soft-detection architecture for 4×4 64-QAM MIMO system. - Pankaj Bhagawat; Rajballav Dash; Gwan Choi (DATE, 2009)

Energy-efficient MIMO detection using unequal error protection for embedded joint decoding system. - Yoon Seok Yang; Pankaj Bhagawat; Gwan Choi (DAC, 2011)