Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages. - Abhijit Chatterjee; Rathish Jayabharathi; Pankaj Pant; Jacob A. Abraham (VTS, 1996)

Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks. - Pankaj Pant; Vivek De; Abhijit Chatterjee (DAC, 1997)

Efficient diagnosis of path delay faults in digital logic circuits. - Pankaj Pant; Abhijit Chatterjee (ICCAD, 1999)

An architectural solution for the inductive noise problem due to clock-gating. - Mondira Deb Pant; Pankaj Pant; D. Scott Wills; Vivek Tiwari (ISLPED, 1999)

Path-delay fault diagnosis in non-scan sequential circuits with at-speed test application. - Pankaj Pant; Abhijit Chatterjee (ITC, 2000)

Inductive Noise Reduction at the Architectural Level. - Mondira Deb Pant; Pankaj Pant; D. Scott Wills; Vivek Tiwari (VLSI Design, 2000)

Path delay fault diagnosis in combinational circuits with implicitfault enumeration. - Pankaj Pant; Yuan-Chieh Hsu; Sandeep K. Gupta 001; Abhijit Chatterjee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

On-chip decoupling capacitor optimization using architectural level prediction. - Mondira Deb Pant; Pankaj Pant; D. Scott Wills (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Voltage transient detection and induction for debug and test. - Rex Petersen; Pankaj Pant; Pablo Lopez; Aaron Barton; Jim Ignowski; Doug Josephson (ITC, 2009)

Understanding Power Supply Droop during At-Speed Scan Testing. - Pankaj Pant; Joshua Zelman (VTS, 2009)

Lessons from at-speed scan deployment on an Intel® Itanium® microprocessor. - Pankaj Pant; Joshua Zelman; Glenn Colón-Bonet; Jennifer Flint; Steve Yurash (ITC, 2010)

Hardware hooks for transition scan characterization. - Pankaj Pant; Eric Skeels (ITC, 2011)

Lateral coupling faults in multi-ported register files and methods for their testing. - Dilip Bhavsar; Michael Lohmiller; Pankaj Pant (VTS, 2016)

Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs. - Jean-François Côté; Mark Kassab; Wojciech Janiszewski; Ricardo Rodrigues 008; Reinhard Meier; Bartosz Kaczmarek; Peter Orlando; Geir Eide; Janusz Rajski; Glenn Colón-Bonet; Naveen Mysore; Ya Yin; et al. (ITC, 2020)

Maximizing Stress Coverage by Novel DFT Techniques and Relaxed Timing Closure. - Arani Sinha; Glenn Colón-Bonet; Michael Fahy; Pankaj Pant; Haijing Mao; Akhilesh Shukla (ITC, 2023)

From Hybrid to Integrated: The Evolution of DFT Integration in SoC Design at Intel. - Brian Pajak; Pankaj Pant; Vidya Neerkundar (ITC, 2024)

Functional State Extraction using Scan DFT. - Ilya Wagner; Pankaj Pant; Arani Sinha (ITC, 2024)