SKIVA: Flexible and Modular Side-channel and Fault Countermeasures. - Pantea Kiaei; Darius Mercadier; Pierre-Évariste Dagand; Karine Heydemann; Patrick Schaumont (IACR Cryptol. ePrint Arch., 2019)

Custom Instruction Support for Modular Defense against Side-channel and Fault Attacks. - Pantea Kiaei; Darius Mercadier; Pierre-Évariste Dagand; Karine Heydemann; Patrick Schaumont (IACR Cryptol. ePrint Arch., 2020)

Domain-Oriented Masked Instruction Set Architecture for RISC-V. - Pantea Kiaei; Patrick Schaumont (IACR Cryptol. ePrint Arch., 2020)

Rewrite to Reinforce: Rewriting the Binary to Apply Countermeasures against Fault Injection. - Pantea Kiaei; Cees-Bart Breunesse; Mohsen Ahmadi; Patrick Schaumont; Jasper Van Woudenberg (DAC, 2021)

SN4KE: Practical Mutation Testing at Binary Level. - Mohsen Ahmadi; Pantea Kiaei; Navid Emamdoost (CoRR, 2021)

Programmable RO (PRO): A Multipurpose Countermeasure against Side-channel and Fault Injection Attack. - Yuan Yao; Pantea Kiaei; Richa Singh 003; Shahin Tajik; Patrick Schaumont (CoRR, 2021)

Real-time Detection and Adaptive Mitigation of Power-based Side-Channel Leakage in SoC. - Pantea Kiaei; Yuan Yao; Patrick Schaumont (CoRR, 2021)

Dimming Down LED: An Open-source Threshold Implementation on Light Encryption Device (LED) Block Cipher. - Yuan Yao; Mo Yang; Pantea Kiaei; Patrick Schaumont (CoRR, 2021)

Synthesis of Parallel Synchronous Software. - Pantea Kiaei; Patrick Schaumont (IEEE Embed. Syst. Lett., 2021)

Saidoyoki: Evaluating side-channel leakage in pre- and post-silicon setting. - Pantea Kiaei; Zhenyuan Liu; Ramazan Kaan Eren; Yuan Yao; Patrick Schaumont (IACR Cryptol. ePrint Arch., 2021)

Programmable RO (PRO): A Multipurpose Countermeasure against Side-channel and Fault Injection Attacks. - Yuan Yao; Pantea Kiaei; Richa Singh 003; Shahin Tajik; Patrick Schaumont (IACR Cryptol. ePrint Arch., 2021)

Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment. - Pantea Kiaei; Zhenyuan Liu; Patrick Schaumont (ACM Great Lakes Symposium on VLSI, 2022)

Gate-Level Side-Channel Leakage Assessment with Architecture Correlation Analysis. - Pantea Kiaei; Yuan Yao; Zhenyuan Liu; Nicole Fern; Cees-Bart Breunesse; Jasper Van Woudenberg; Kate Gillis; Alex Dich; Peter Grossmann; Patrick Schaumont (CoRR, 2022)

SoC Root Canal! Root Cause Analysis of Power Side-Channel Leakage in System-on-Chip Designs. - Pantea Kiaei; Patrick Schaumont (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022)

Architecture Support for Bitslicing. - Pantea Kiaei; Thomas Conroy; Patrick Schaumont (IEEE Trans. Emerg. Top. Comput., 2023)

Gate-Level Side-Channel Leakage Ranking With Architecture Correlation Analysis. - Pantea Kiaei; Yuan Yao; Zhenyuan Liu; Nicole Fern; Cees-Bart Breunesse; Jasper Van Woudenberg; Kate Gillis; Alex Dich; Peter Grossmann; Patrick Schaumont (IEEE Trans. Emerg. Top. Comput., 2024)