A multi-format Blu-ray player SoC in 90nm CMOS. - Chi-Cheng Ju; Tsu-Ming Liu; Chih-Chieh Yang; Shih-Hung Lin; Kuo-Pin Lan; Chien-Hua Wu; Ting-Hsun Wei; Chi-Chin Lien; Jiun-Yuan Wu; Chih-Hao Hsiao; Te-Wei Chen; Yeh-Lin Chu; et al. (ISSCC, 2009)

A 28fJ/conv-step CT ΔΣ modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer. - Yun-Shiang Shu; Jui-Yuan Tsai; Ping Chen; Tien-Yu Lo; Pao-Cheng Chiu (ISSCC, 2013)

A background calibration technique for fully dynamic flash ADCs. - Yun-Shiang Shu; Jui-Yuan Tsai; Ping Chen; Tien-Yu Lo; Pao-Cheng Chiu (VLSI-DAT, 2013)

A 960MS/s DAC with 80dB SFDR in 20nm CMOS for multi-mode baseband wireless transmitter. - Wei-Hsin Tseng; Pao-Cheng Chiu (VLSIC, 2014)

A 12-bit 104-MS/s SAR ADC in 28nm CMOS for digitally-assisted wireless transmitters. - Wei-Hsin Tseng; Wei-Liang Lee; Chang-Yang Huang; Pao-Cheng Chiu (A-SSCC, 2015)

A 16nm FinFet 19/39MHz 78/72dB DR noise-injected aggregated CTSDM ADC for configurable LTE advanced CCA/NCCA Application. - Tsung-Kai Kao; Ping Chen; Jui-Yuan Tsai; Pao-Cheng Chiu (VLSIC, 2015)

A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters. - Wei-Hsin Tseng; Wei-Liang Lee; Chang-Yang Huang; Pao-Cheng Chiu (IEEE J. Solid State Circuits, 2016)

An 8 × - OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT Δ σ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS. - Tien-Yu Lo; Chan-Hsiang Weng; Hung-Yi Hsieh; Yun-Shiang Shu; Pao-Cheng Chiu (ISSCC, 2019)