On-Die Supply-Resonance Suppression Using Band-Limited Active Damping. - Jianping Xu; Peter Hazucha; Mingwei Huang; Paolo A. Aseron; Fabrice Paillet; Gerhard Schrom; James W. Tschanz; Cangsang Zhao; Vivek De; Tanay Karnik; Greg Taylor (ISSCC, 2007)

2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. - Dinesh Somasekhar; Yibin Ye; Paolo A. Aseron; Shih-Lien Lu; Muhammad M. Khellah; Jason Howard; Gregory Ruhl; Tanay Karnik; Shekhar Y. Borkar; Vivek De; Ali Keshavarzi (ISSCC, 2008)

A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction. - Jianping Xu; Peter Hazucha; Zuoguo Wu; Paolo A. Aseron; Mingwei Huang; Fabrice Paillet; Gerhard Schrom; James W. Tschanz; Vivek De; Tanay Karnik; Greg Taylor (IEEE J. Solid State Circuits, 2008)

2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. - Dinesh Somasekhar; Yibin Ye; Paolo A. Aseron; Shih-Lien Lu; Muhammad M. Khellah; Jason Howard; Gregory Ruhl; Tanay Karnik; Shekhar Borkar; Vivek K. De; Ali Keshavarzi (IEEE J. Solid State Circuits, 2009)

Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. - Keith A. Bowman; Carlos Tokunaga; James W. Tschanz; Arijit Raychowdhury; Muhammad M. Khellah; Bibiche M. Geuskens; Shih-Lien Lu; Paolo A. Aseron; Tanay Karnik; Vivek De (CICC, 2010)

Resilient microprocessor design for high performance & energy efficiency. - Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Arijit Raychowdhury; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek De (ISLPED, 2010)

Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. - Saurabh Dighe; Sriram R. Vangal; Paolo A. Aseron; Shasi Kumar; Tiju Jacob; Keith A. Bowman; Jason Howard; James W. Tschanz; Vasantha Erraguntla; Nitin Borkar; Vivek De; Shekhar Borkar (ISSCC, 2010)

A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. - James W. Tschanz; Keith A. Bowman; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Arijit Raychowdhury; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek De (ISSCC, 2010)

Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. - Arijit Raychowdhury; Jim Tschanz; Keith A. Bowman; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek De (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. - Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Arijit Raychowdhury; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek K. De (IEEE J. Solid State Circuits, 2011)

Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. - Saurabh Dighe; Sriram R. Vangal; Paolo A. Aseron; Shasi Kumar; Tiju Jacob; Keith A. Bowman; Jason Howard; James W. Tschanz; Vasantha Erraguntla; Nitin Borkar; Vivek K. De; Shekhar Borkar (IEEE J. Solid State Circuits, 2011)

All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. - Keith A. Bowman; Carlos Tokunaga; James W. Tschanz; Arijit Raychowdhury; Muhammad M. Khellah; Bibiche M. Geuskens; Shih-Lien Lu; Paolo A. Aseron; Tanay Karnik; Vivek K. De (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

An IA-32 processor with a wide voltage operating range in 32nm CMOS. - Gregory Ruhl; Saurabh Dighe; Shailendra Jain; Surhud Khare; Satish Yada; V. Ambili; Praveen Salihundam; Shiva Ramani; Sriram Muthukumar; M. Srinivasan; Arun Kumar; Shasi Kumar; et al. (Hot Chips Symposium, 2012)

A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. - Shailendra Jain; Surhud Khare; Satish Yada; V. Ambili; Praveen Salihundam; Shiva Ramani; Sriram Muthukumar; M. Srinivasan; Arun Kumar; Shasi Kumar; Rajaraman Ramanarayanan; Vasantha Erraguntla; et al. (ISSCC, 2012)

4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging. - Jaydeep P. Kulkarni; Carlos Tokunaga; Paolo A. Aseron; Trang Nguyen; Charles Augustine; James W. Tschanz; Vivek De (ISSCC, 2015)

An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS. - Somnath Paul; Vinayak Honkote; Ryan Gary Kim; Turbo Majumder; Paolo A. Aseron; Vaughn Grossnickle; Robert Sankman; Debendra Mallik; Sandeep Jain; Sriram R. Vangal; James W. Tschanz; Vivek De (VLSI Circuits, 2016)

A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging. - Jaydeep P. Kulkarni; Carlos Tokunaga; Paolo A. Aseron; Trang Nguyen; Charles Augustine; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2016)

A Sub-cm3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications. - Somnath Paul; Vinayak Honkote; Ryan Gary Kim; Turbo Majumder; Paolo A. Aseron; Vaughn Grossnickle; Robert Sankman; Debendra Mallik; Tao Wang; Sriram R. Vangal; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2017)

A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS. - Tanay Karnik; Dileep Kurian; Paolo A. Aseron; Richard Dorrance; Erkan Alpman; Angela Nicoara; Roman Popov; Leonid Azarenkov; Mikhail J. Moiseev; Li Zhao 002; Santosh Ghosh; Rafael Misoczki; et al. (ISSCC, 2018)

A Distributed Autonomous and Collaborative Multi-Robot System Featuring a Low-Power Robot SoC in 22nm CMOS for Integrated Battery-Powered Minibots. - Vinayak Honkote; Dileep Kurian; Sriram Muthukumar; Dibyendu Ghosh; Satish Yada; Kartik Jain; Bradley Jackson; Ilya Klotchkov; Mallikarjuna Rao Nimmagadda; Shreela Dattawadkar; Pranjali Deshmukh; Ankit Gupta 011; et al. (ISSCC, 2019)

Design Methodology for Scalable 2.5D/3D Heterogenous Tiled Chiplet Systems. - Srivatsa Rangachar Srinivasa; Jainaveen Sundaram Priya; Dileep Kurian; Erika Ramirez Lozano; Satish Yada; Saransh Chhabra; Kamakhya Prasad Sahu; Paolo A. Aseron; Ronald Kalim; Anuradha Srinivasan; Tanay Karnik (ISQED, 2022)

A 3.2GHz-15GHz Low Jitter Resonant Clock Featuring Rotary Traveling Wave Oscillators in Intel 4 CMOS for 3D Heterogeneous Multi-Die Systems. - Vinayak Honkote; Ragh Kuttappa; Jainaveen Sundaram; Satish Yada; Chinnusamy Kalimuthu; Juhi Patil; Richard Lee; Cristan Paulino; Paolo A. Aseron; Trang Nguyen; Amreesh Rao; Dileep Kurian; et al. (VLSI Technology and Circuits, 2024)

A High-Performance Passive Base System for Distributed AI/Media Acceleration. - Ragh Kuttappa; Jainaveen Sundaram; Srivatsa Rangachar Srinivasa; Paolo A. Aseron; Gauthaman Murali; Vinayak Honkote; Prerna Budhkar; Dileep Kurian; Ronald Kalim; Thomas P. Thomas; Anuradha Srinivasan; Tanay Karnik (CICC, 2025)

A 68 TOPS/W, 256MB SRAM Sparse GEMM Accelerator Tiled Across 16, 4nm Near Memory Compute (NMC) Chiplets Disaggregated 2.5D System. - Srivatsa Rangachar Srinivasa; Prerna Budhkar; Gauthaman Murali; Vui Seng Chua; Paolo A. Aseron; Vinayak Honkote; Ravi R. Iyer 001; Nilesh Jain; Dileep John Kurian; Anuradha Srinivasan; Tanay Karnik (CICC, 2025)

System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution. - Srivatsa Rangachar Srinivasa; Dileep Kurian; Paolo A. Aseron; Prerna Budhkar; Vinayak Honkote; Dan Lake; Jaykant Timbadiya; Satish Yada; Suresh Kadavakollu; James Greensky; Gauthaman Murali; Anuradha Srinivasan; et al. (ACM Great Lakes Symposium on VLSI, 2025)

A 300MB SRAM, 20Tb/s Bandwidth Scalable Heterogenous 2.5D System Inferencing Simultaneous Streams Across 20 Chiplets with Workload-Dependent Configurations. - Srivatsa Rangachar Srinivasa; Dileep Kurian; Paolo A. Aseron; Prerna Budhkar; Arun Radhakrishnan; Alejandro Cardenas Lopez; Jainaveen Sundaram; Vinayak Honkote; Leonid Azarenkov; Dan Lake; Jaykant Timbadiya; Mikhail J. Moiseev; et al. (ISSCC, 2025)