A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories. - Paolo Bernardi 002; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (DATE, 2003)

An efficient algorithm for the extraction of compressed diagnostic information from embedded memory cores. - Paolo Bernardi 002; Maurizio Rebaudengo; Matteo Sonza Reorda (ETFA (1), 2003)

Analyzing SEU Effects in SRAM-based FPGAs. - Massimo Violante; M. Ceschia; Matteo Sonza Reorda; Alessandro Paccagnella; Paolo Bernardi 002; Maurizio Rebaudengo; D. Bortolato; M. Bellato; P. Zambolin; A. Candelori (IOLTS, 2003)

Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores. - Davide Appello; Paolo Bernardi 002; Alessandra Fudoli; Maurizio Rebaudengo; Matteo Sonza Reorda; Vincenzo Tancorre; Massimo Violante (ITC, 2003)

Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA. - M. Bellato; Paolo Bernardi 002; D. Bortolato; A. Candelori; M. Ceschia; Alessandro Paccagnella; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante; P. Zambolin (DATE, 2004)

Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study. - Paolo Bernardi 002; Guido Masera; Federico Quaglio; Matteo Sonza Reorda (DATE, 2004)

Exploiting an I-IP for In-Field SOC Test. - Paolo Bernardi 002; Maurizio Rebaudengo; Matteo Sonza Reorda (DFT, 2004)

On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs. - Paolo Bernardi 002; Matteo Sonza Reorda; Luca Sterpone; Massimo Violante (IOLTS, 2004)

Using Infrastructure IPs to Support SW-Based Self-Test of Processor Cores. - Paolo Bernardi 002; Maurizio Rebaudengo; Matteo Sonza Reorda (MTV, 2004)

A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. - Davide Appello; Alessandra Fudoli; Vincenzo Tancorre; Paolo Bernardi 002; Fulvio Corno; Maurizio Rebaudengo; Matteo Sonza Reorda (J. Electron. Test., 2004)

An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors. - Paolo Bernardi 002; Letícia Maria Veiras Bolzani; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (DFT, 2005)

On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core. - Paolo Bernardi 002; Letícia Maria Veiras Bolzani; Maurizio Rebaudengo; Matteo Sonza Reorda; Fabian Vargas 001; Massimo Violante (DSN, 2005)

Exploiting an infrastructure IP to reduce memory diagnosis costs in SoCs. - Paolo Bernardi 002; Michelangelo Grosso; Maurizio Rebaudengo; Matteo Sonza Reorda (ETS, 2005)

Integrating BIST Techniques for On-Line SoC Testing. - Alberto Manzone; Paolo Bernardi 002; Michelangelo Grosso; Maurizio Rebaudengo; Ernesto Sánchez 001; Matteo Sonza Reorda (IOLTS, 2005)

Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores. - Paolo Bernardi 002; Michelangelo Grosso; Maurizio Rebaudengo; Matteo Sonza Reorda (MTV, 2005)

Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets. - Paolo Bernardi 002; Ernesto Sánchez 001; Massimiliano Schillaci; Matteo Sonza Reorda; Giovanni Squillero (MTV, 2005)

An Evolutionary Methodology to Enhance Processor Software-Based Diagnosis. - Paolo Bernardi 002; Ernesto Sánchez 001; Massimiliano Schillaci; Giovanni Squillero; Matteo Sonza Reorda (IEEE Congress on Evolutionary Computation, 2006)

An effective technique for minimizing the cost of processor software-based diagnosis in SoCs. - Paolo Bernardi 002; Ernesto Sánchez 001; Massimiliano Schillaci; Giovanni Squillero; Matteo Sonza Reorda (DATE, 2006)

Test Considerations about the Structured ASIC Paradigm. - Paolo Bernardi 002; Michelangelo Grosso (DDECS, 2006)

Embedded Memory Diagnosis: An Industrial Workflow. - Davide Appello; Vincenzo Tancorre; Paolo Bernardi 002; Michelangelo Grosso; Maurizio Rebaudengo; Matteo Sonza Reorda (ITC, 2006)

Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications. - Paolo Bernardi 002; Letícia Maria Veiras Bolzani; Alberto Manzone; Massimo Osella; Massimo Violante; Matteo Sonza Reorda (MTV, 2006)

On the Automation of the Test Flow of Complex SoCs. - Davide Appello; Vincenzo Tancorre; Paolo Bernardi 002; Michelangelo Grosso; Maurizio Rebaudengo; Matteo Sonza Reorda (VTS, 2006)

A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries. - Paolo Bernardi 002; Michelangelo Grosso; Maurizio Rebaudengo; Matteo Sonza Reorda (VTS, 2006)

System-in-Package Testing: Problems and Solutions. - Davide Appello; Paolo Bernardi 002; Michelangelo Grosso; Matteo Sonza Reorda (IEEE Des. Test Comput., 2006)

A New Hybrid Fault Detection Technique for Systems-on-a-Chip. - Paolo Bernardi 002; Letícia Maria Veiras Bolzani; Maurizio Rebaudengo; Matteo Sonza Reorda; Fabian Vargas 001; Massimo Violante (IEEE Trans. Computers, 2006)

Agri-Food Traceability Management using a RFID System with Privacy Protection. - Paolo Bernardi 002; Claudio Demartini; Filippo Gandino; Bartolomeo Montrucchio; Maurizio Rebaudengo; Erwing Ricardo Sanchez (AINA, 2007)

Extended Fault Detection Techniques for Systems-on-Chip. - Paolo Bernardi 002; Letícia Maria Veiras Bolzani; Matteo Sonza Reorda (DDECS, 2007)

An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains. - Jorge Luis Lagos-Benites; Davide Appello; Paolo Bernardi 002; Michelangelo Grosso; Danilo Ravotto; Edgar E. Sánchez; Matteo Sonza Reorda (DFT, 2007)

On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores. - Paolo Bernardi 002; Michelangelo Grosso; Ernesto Sánchez 001; Matteo Sonza Reorda (ETS, 2007)

Design of an UHF RFID transponder for secure authentication. - Paolo Bernardi 002; Filippo Gandino; Bartolomeo Montrucchio; Maurizio Rebaudengo; Erwing Ricardo Sanchez (ACM Great Lakes Symposium on VLSI, 2007)

Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems. - Paolo Bernardi 002; Michelangelo Grosso; Matteo Sonza Reorda (ACM Great Lakes Symposium on VLSI, 2007)

A Hybrid Approach to Fault Detection and Correction in SoCs. - Paolo Bernardi 002; Letícia Maria Veiras Bolzani; Matteo Sonza Reorda (IOLTS, 2007)

An optimized hybrid approach to provide fault detection and correction in SoCs. - Letícia Maria Veiras Bolzani; Paolo Bernardi 002; Matteo Sonza Reorda (SBCCI, 2007)

A System-layer Infrastructure for SoC Diagnosis. - Paolo Bernardi 002; Michelangelo Grosso; Maurizio Rebaudengo; Matteo Sonza Reorda (J. Electron. Test., 2007)

An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers. - Paolo Bernardi 002; Matteo Sonza Reorda (DATE, 2008)

SoC Symbolic Simulation: a case study on delay fault testing. - Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Paolo Bernardi 002 (DDECS, 2008)

An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs. - Davide Appello; Paolo Bernardi 002; R. Cagliesi; M. Giancarlini; Michelangelo Grosso (ETS, 2008)

Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors. - Paolo Bernardi 002; Kyriakos Christou; Michelangelo Grosso; Maria K. Michael; Ernesto Sánchez 001; Matteo Sonza Reorda (EvoWorkshops, 2008)

Robust Design-for-Productization Practices for High Quality Automotive Products. - Paolo Bernardi 002; Fabio Melchiori; Davide Pandini; Santo Pugliese; Davide Appello (ITC, 2008)

A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores. - Paolo Bernardi 002; Michelangelo Grosso; Ernesto Sánchez 001; Matteo Sonza Reorda (MTV, 2008)

A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions. - Kyriakos Christou; Maria K. Michael; Paolo Bernardi 002; Michelangelo Grosso; Ernesto Sánchez 001; Matteo Sonza Reorda (VTS, 2008)

An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores. - Paolo Bernardi 002; Ernesto Sánchez 001; Massimiliano Schillaci; Giovanni Squillero; Matteo Sonza Reorda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

An efficient fault simulation technique for transition faults in non-scan sequential circuits. - Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Paolo Bernardi 002; Matteo Sonza Reorda (DDECS, 2009)

An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs. - Lyl M. Ciganda; Francesco Abate; Paolo Bernardi 002; M. Bruno; Matteo Sonza Reorda (DDECS, 2009)

Automatic Functional Stress Pattern Generation for SoC Reliability Characterization. - Davide Appello; Paolo Bernardi 002; R. Cagliesi; M. Giancarlini; Michelangelo Grosso; Edgar E. Sánchez; Matteo Sonza Reorda (ETS, 2009)

An I-IP based approach for the monitoring of NBTI effects in SoCs. - C. Guardiani; A. Shibkov; Angelo Brambilla; Giancarlo Storti Gajani; Davide Appello; Fausto Piazza; Paolo Bernardi 002 (IOLTS, 2009)

Evaluating Alpha-induced soft errors in embedded microprocessors. - Paolo Rech; Simone Gerardin; Alessandro Paccagnella; Paolo Bernardi 002; Michelangelo Grosso; Matteo Sonza Reorda; Davide Appello (IOLTS, 2009)

DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study. - Davide Appello; Paolo Bernardi 002; Simone Gerardin; Michelangelo Grosso; Alessandro Paccagnella; Paolo Rech; Matteo Sonza Reorda (VTS, 2009)

Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-Scan SOCs. - Davide Appello; Paolo Bernardi 002; Michelangelo Grosso; Ernesto Sánchez 001; Matteo Sonza Reorda (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Cumulative embedded memory failure bitmap display & analysis. - Nicola Campanelli; Tamas Kerekes; Paolo Bernardi 002; Mauricio de Carvalho; Alessandro Panariti; Matteo Sonza Reorda; Davide Appello; Mario Barone (DDECS, 2010)

An Exact and Efficient Critical Path Tracing Algorithm. - Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Paolo Bernardi 002; Matteo Sonza Reorda (DELTA, 2010)

An adaptive tester architecture for volume diagnosis. - Paolo Bernardi 002; Michelangelo Grosso; Matteo Sonza Reorda (ETS, 2010)

A programmable BIST for DRAM testing and diagnosis. - Paolo Bernardi 002; Michelangelo Grosso; Matteo Sonza Reorda; Y. Zhang (ITC, 2010)

A tester architecture suitable for MEMS calibration and testing. - Lyl M. Ciganda Brasca; Paolo Bernardi 002; Matteo Sonza Reorda; Dimitri Barbieri; Maurizio Straiotto; Luciano Bonaria (ITC, 2010)

A Fault Grading Methodology for Software-Based Self-Test Programs in Systems-on-Chip. - Oscar Ballan; Paolo Bernardi 002; Giovanni Fontana; Michelangelo Grosso; Ernesto Sánchez 001 (MTV, 2010)

An Enhanced Strategy for Functional Stress Pattern Generation for System-on-Chip Reliability Characterization. - Mauricio de Carvalho; Paolo Bernardi 002; Ernesto Sánchez 001; Matteo Sonza Reorda (MTV, 2010)

Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug. - Paolo Bernardi 002; Michelangelo Grosso; Maurizio Rebaudengo; Matteo Sonza Reorda (IET Comput. Digit. Tech., 2010)

A Hybrid Approach for Detection and Correction of Transient Faults in SoCs. - Paolo Bernardi 002; Letícia Maria Veiras Bolzani Poehls; Michelangelo Grosso; Matteo Sonza Reorda (IEEE Trans. Dependable Secur. Comput., 2010)

A New Architecture to Cross-Fertilize On-Line and Manufacturing Testing. - Paolo Bernardi 002; Matteo Sonza Reorda (Asian Test Symposium, 2011)

Fault grading of software-based self-test procedures for dependable automotive applications. - Paolo Bernardi 002; Michelangelo Grosso; Ernesto Sánchez 001; Oscar Ballan (DATE, 2011)

Optimized embedded memory diagnosis. - Mauricio de Carvalho; Paolo Bernardi 002; Matteo Sonza Reorda; Nicola Campanelli; Tamas Kerekes; Davide Appello; Mario Barone; Vincenzo Tancorre; Marco Terzi (DDECS, 2011)

On the Modeling of Gate Delay Faults by Means of Transition Delay Faults. - Paolo Bernardi 002; Matteo Sonza Reorda; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch (DFT, 2011)

An effective methodology for on-line testing of embedded microprocessors. - Paolo Bernardi 002; Lyl M. Ciganda; Ernesto Sánchez 001; Matteo Sonza Reorda (IOLTS, 2011)

A Parallel Tester Architecture for Accelerometer and Gyroscope MEMS Calibration and Test. - Lyl M. Ciganda Brasca; Paolo Bernardi 002; Matteo Sonza Reorda; Dimitri Barbieri; Luciano Bonaria; Roberto Losco; Luciano Marcigot; Maurizio Straiotto (J. Electron. Test., 2011)

Peak Power Estimation: A Case Study on CPU Cores. - Paolo Bernardi 002; Mauricio de Carvalho; Ernesto Sánchez 001; Matteo Sonza Reorda; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Miroslav Valka (Asian Test Symposium, 2012)

A SBST strategy to test microprocessors' Branch Target Buffer. - Paolo Bernardi 002; Lyl M. Ciganda; Michelangelo Grosso; Ernesto Sánchez 001; Matteo Sonza Reorda (DDECS, 2012)

On-line software-based self-test of the Address Calculation Unit in RISC processors. - Paolo Bernardi 002; Lyl M. Ciganda; Mauricio de Carvalho; Michelangelo Grosso; Jorge Luis Lagos-Benites; Ernesto Sánchez 001; Matteo Sonza Reorda; Oscar Ballan (ETS, 2012)

An Adaptive Low-Cost Tester Architecture Supporting Embedded Memory Volume Diagnosis. - Paolo Bernardi 002; Lyl M. Ciganda (IEEE Trans. Instrum. Meas., 2012)

An Efficient Method for the Test of Embedded Memory Cores during the Operational Phase. - Paolo Bernardi 002; Lyl M. Ciganda; Matteo Sonza Reorda; Said Hamdioui (Asian Test Symposium, 2013)

On-line functionally untestable fault identification in embedded processor cores. - Paolo Bernardi 002; Michele Bonazza; Ernesto Sánchez 001; Matteo Sonza Reorda; Oscar Ballan (DATE, 2013)

A functional test algorithm for the register forwarding and pipeline interlocking unit in pipelined microprocessors. - Paolo Bernardi 002; D. Boyang; Lyl M. Ciganda; Ernesto Sánchez 001; Matteo Sonza Reorda; Michelangelo Grosso; Oscar Ballan (IDT, 2013)

A software-based self-test strategy for on-line testing of the scan chain circuitries in embedded microprocessors. - Oscar Ballan; Paolo Bernardi 002; B. Yazdani; Ernesto Sánchez 001 (IOLTS, 2013)

Increasing fault coverage during functional test in the operational phase. - Mauricio de Carvalho; Paolo Bernardi 002; Ernesto Sánchez 001; Matteo Sonza Reorda; Oscar Ballan (IOLTS, 2013)

On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors. - Paolo Bernardi 002; Riccardo Cantoro; Lyl M. Ciganda Brasca; Boyang Du; Ernesto Sánchez 001; Matteo Sonza Reorda; Michelangelo Grosso; Oscar Ballan (MTV, 2013)

Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption. - Paolo Bernardi 002; Mauricio de Carvalho; Ernesto Sánchez 001; Matteo Sonza Reorda; Alberto Bosio; Luigi Dilillo; Miroslav Valka; Patrick Girard 001 (J. Low Power Electron., 2013)

An effective approach to automatic functional processor test generation for small-delay faults. - Andreas Riefert; Lyl M. Ciganda; Matthias Sauer 002; Paolo Bernardi 002; Matteo Sonza Reorda; Bernd Becker 001 (DATE, 2014)

An intra-cell defect grading tool. - Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri-Sanial; Arnaud Virazel; S. Bernabovi; Paolo Bernardi 002 (DDECS, 2014)

On the in-field functional testing of decode units in pipelined RISC processors. - Paolo Bernardi 002; Riccardo Cantoro; Lyl M. Ciganda Brasca; Ernesto Sánchez 001; Matteo Sonza Reorda; Sergio de Luca; Renato Meregalli; Alessandro Sansonetti (DFT, 2014)

A Comprehensive Evaluation of Functional Programs for Power-Aware Test. - Aymen Touati; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri-Sanial; Arnaud Virazel; Paolo Bernardi 002 (NATW, 2014)

Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test. - Mauricio de Carvalho; Paolo Bernardi 002; Ernesto Sánchez 001; Matteo Sonza Reorda; Oscar Ballan (J. Electron. Test., 2014)

MIHST: A Hardware Technique for Embedded Microprocessor Functional On-Line Self-Test. - Paolo Bernardi 002; Lyl Mercedes Ciganda; Ernesto Sánchez 001; Matteo Sonza Reorda (IEEE Trans. Computers, 2014)

Exploring the impact of functional test programs re-used for power-aware testing. - Aymen Touati; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Arnaud Virazel; Paolo Bernardi 002; Matteo Sonza Reorda (DATE, 2015)

An effective ATPG flow for Gate Delay Faults. - Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Arnaud Virazel; Paolo Bernardi 002; Matteo Sonza Reorda (DTIS, 2015)

Scan-chain intra-cell defects grading. - Aymen Touati; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Arnaud Virazel; Paolo Bernardi 002; Matteo Sonza Reorda (DTIS, 2015)

Software-based self-test techniques of computational modules in dual issue embedded processors. - Paolo Bernardi 002; C. Bovi; Riccardo Cantoro; Sergio de Luca; Renato Meregalli; Davide Piumatti; Ernesto Sánchez 001; Alessandro Sansonetti (ETS, 2015)

SW-based transparent in-field memory testing. - Paolo Bernardi 002; Lyl M. Ciganda Brasca; Matteo Sonza Reorda; Said Hamdioui (LATS, 2015)

An effective approach for functional test programs compaction. - Aymen Touati; Alberto Bosio; Patrick Girard 001; Arnaud Virazel; Paolo Bernardi 002; Matteo Sonza Reorda (DDECS, 2016)

In-field functional test programs development flow for embedded FPUs. - Riccardo Cantoro; Davide Piumatti; Paolo Bernardi 002; Sergio de Luca; Alessandro Sansonetti (DFT, 2016)

Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study. - Aymen Touati; Alberto Bosio; Patrick Girard 001; Arnaud Virazel; Paolo Bernardi 002; Matteo Sonza Reorda (ISVLSI, 2016)

Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs. - Paolo Bernardi 002; Alberto Bosio; Giorgio Di Natale; Andrea Guerriero; Ernesto Sánchez 001; Federico Venini (VLSI-SoC (Selected Papers), 2016)

Faster-than-at-speed execution of functional programs: An experimental analysis. - Paolo Bernardi 002; Alberto Bosio; Giorgio Di Natale; Andrea Guerriero; Federico Venini (VLSI-SoC, 2016)

Thermal issues in test: An overview of the significant aspects and industrial practice. - Juergen Alt; Paolo Bernardi 002; Alberto Bosio; Riccardo Cantoro; Hans G. Kerkhoff; Andreas Leininger; Wolfgang Molzer; Alessandro Motta; Christian Pacha; Alberto Pagani; Alireza Rohani; R. Strasser (VTS, 2016)

Development Flow for On-Line Core Self-Test of Automotive Microcontrollers. - Paolo Bernardi 002; Riccardo Cantoro; Sergio de Luca; Ernesto Sánchez 001; Alessandro Sansonetti (IEEE Trans. Computers, 2016)

A comprehensive methodology for stress procedures evaluation and comparison for Burn-In of automotive SoC. - Davide Appello; Paolo Bernardi 002; G. Giacopelli; Alessandro Motta; Alberto Pagani; Giorgio Pollaccia; C. Rabbi; Marco Restifo; P. Ruberg; Ernesto Sánchez 001; C. M. Villa; Federico Venini (DATE, 2017)

On-line software-based self-test for ECC of embedded RAM memories. - Marco Restifo; Paolo Bernardi 002; Sergio de Luca; Alessandro Sansonetti (DFT, 2017)

An effective fault-injection framework for memory reliability enhancement perspectives. - G. Harcha; Alberto Bosio; Patrick Girard 001; Arnaud Virazel; Paolo Bernardi 002 (DTIS, 2017)

Robustness in automotive electronics: An industrial overview of major concerns. - Ulrich Backhausen; Oscar Ballan; Paolo Bernardi 002; Sergio de Luca; Julie Henzler; Thomas Kern; Davide Piumatti; Thomas Rabenalt; Krishnapriya Chakiat Ramamoorthy; Ernesto Sánchez 001; Alessandro Sansonetti; Rudolf Ullmann; et al. (IOLTS, 2017)

On the in-field test of embedded memories. - Paolo Bernardi 002; Marco Restifo; Ernesto Sánchez 001; Matteo Sonza Reorda (IOLTS, 2017)

A DMA and CACHE-based stress schema for burn-in of automotive microcontroller. - Paolo Bernardi 002; Riccardo Cantoro; L. Gianotto; Marco Restifo; Ernesto Sánchez 001; Federico Venini; Davide Appello (LATS, 2017)

On the in-field testing of spare modules in automotive microprocessors. - Paolo Bernardi 002; Sergio de Luca; Davide Piumatti; S. Regis; Ernesto Sánchez 001; Alessandro Sansonetti (VLSI-SoC, 2017)

Microprocessor Testing: Functional Meets Structural Test. - Aymen Touati; Alberto Bosio; Patrick Girard 001; Arnaud Virazel; Paolo Bernardi 002; Matteo Sonza Reorda (J. Circuits Syst. Comput., 2017)

An Optimized Test During Burn-In for Automotive SoC. - Davide Appello; Conrad Bugeja; Giorgio Pollaccia; Paolo Bernardi 002; Riccardo Cantoro; Marco Restifo; Ernesto Sánchez 001; Federico Venini (IEEE Des. Test, 2018)

Adaptive Management Techniques for Optimized Burn-in of Safety-Critical SoC. - Davide Appello; Paolo Bernardi 002; Conrad Bugeja; Riccardo Cantoro; Giorgio Pollaccia; Marco Restifo; Federico Venini (J. Electron. Test., 2018)

An Evolutionary Algorithm Approach to Stress Program Generation During Burn-In. - Davide Appello; Paolo Bernardi 002; Conrad Bugeja; Riccardo Cantoro; Andrea Colazzo; Alessandro Motta; Alberto Pagani; Giorgio Pollaccia; Marco Restifo; Ernesto Sánchez 001; Federico Venini (J. Low Power Electron., 2018)

Scan-Chain Intra-Cell Aware Testing. - Aymen Touati; Alberto Bosio; Patrick Girard 001; Arnaud Virazel; Paolo Bernardi 002; Matteo Sonza Reorda; Etienne Auvray (IEEE Trans. Emerg. Top. Comput., 2018)

Non-Intrusive Self-Test Library for Automotive Critical Applications: Constraints and Solutions. - Paolo Bernardi 002; Riccardo Cantoro; Andrea Floridia; Davide Piumatti; C. Pogonea; Annachiara Ruospo; Ernesto Sánchez 001; Sergio de Luca; Alessandro Sansonetti (DATE, 2019)

Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test. - F. Almeida; Paolo Bernardi 002; D. Calabrese; Marco Restifo; Matteo Sonza Reorda; Davide Appello; Giorgio Pollaccia; Vincenzo Tancorre; Roberto Ugioli; Gulio Zoppi (DDECS, 2019)

A Hybrid In-Field Self-Test Technique for SoCs. - Sara Carbonara; Paolo Bernardi 002; Marco Restifo (DTIS, 2019)

A Machine Learning-based Approach to Optimize Repair and Increase Yield of Embedded Flash Memories in Automotive Systems-on-Chip. - A. Manzini; P. Inglese; L. Caldi; R. Cantero; G. Carnevale; M. Coppetta; M. Giltrelli; N. Mautone; F. Irrera; Rudolf Ullmann; Paolo Bernardi 002 (ETS, 2019)

Facilitating Fault-Simulation Comprehension through a Fault-Lists Analysis Tool. - Paolo Bernardi 002; Davide Piumatti; Ernesto Sánchez 001 (LASCAS, 2019)

A Reliability Analysis of a Deep Neural Network. - Alberto Bosio; Paolo Bernardi 002; Annachiara Ruospo; Ernesto Sánchez 001 (LATS, 2019)

Exploring the Mysteries of System-Level Test. - Ilia Polian; Jens Anders; Steffen Becker 001; Paolo Bernardi 002; Krishnendu Chakrabarty; Nourhan Elhamawy; Matthias Sauer 002; Adit D. Singh; Matteo Sonza Reorda; Stefan Wagner 001 (ATS, 2020)

Applicative System Level Test introduction to Increase Confidence on Screening Quality. - Paolo Bernardi 002; Marco Restifo; Matteo Sonza Reorda; Davide Appello; Claudia Bertani; D. Petrali (DDECS, 2020)

Software-Based Self-Test Techniques for Dual-Issue Embedded Processors. - Paolo Bernardi 002; Riccardo Cantoro; Sergio de Luca; Ernesto Sánchez 001; Alessandro Sansonetti; Giovanni Squillero (IEEE Trans. Emerg. Top. Comput., 2020)

Accelerated Analysis of Simulation Dumps through Parallelization on Multicore Architectures. - Davide Appello; Paolo Bernardi 002; Andrea Calabrese; Stefano Littardi; Giorgio Pollaccia; Stefano Quer; Vincenzo Tancorre; Roberto Ugioli (DDECS, 2021)

Industrial best practice: cases of study by automotive chip- makers. - L. Degli Abbati; Rudolf Ullmann; G. Paganini; M. Coppetta; L. Zaia; Vincent Huard; Olivier Montfort; Riccardo Cantoro; Giorgio Insinga; F. Venini; P. Calao; Paolo Bernardi 002 (DFT, 2021)

Innovative methods for Burn-In related Stress Metrics Computation. - Walter Ruggeri; Paolo Bernardi 002; Stefano Littardi; Matteo Sonza Reorda; Davide Appello; Claudia Bertani; Giorgio Pollaccia; Vincenzo Tancorre; Roberto Ugioli (DTIS, 2021)

System-Level Test: State of the Art and Challenges. - Davide Appello; H. H. Chen; Matthias Sauer 002; Ilia Polian; Paolo Bernardi 002; Matteo Sonza Reorda (IOLTS, 2021)

Online scheduling of concurrent Memory BISTs execution at Real-Time Operating-System level. - Francesco Angione; Paolo Bernardi 002; Gabriele Filipponi; Claudia Tempesta; Matteo Sonza Reorda; Davide Appello; Vincenzo Tancorre; Roberto Ugioli (DFT, 2022)

Test, Reliability and Functional Safety Trends for Automotive System-on-Chip. - Francesco Angione; Davide Appello; Joseph Aribido; Jyotika Athavale; Nicolò Bellarmino; Paolo Bernardi 002; Riccardo Cantoro; Corrado De Sio; Tommaso Foscale; Gabriele Gavarini; Juan-David Guerrero-Balaguera; Martin Huch; et al. (ETS, 2022)

An Optimized Burn-In Stress Flow targeting Interconnections logic to Embedded Memories in Automotive Systems-on-Chip. - Francesco Angione; Paolo Bernardi 002; Gabriele Filipponi; Matteo Sonza Reorda; Davide Appello; Vincenzo Tancorre; Roberto Ugioli (ETS, 2022)

Optimized diagnostic strategy for embedded memories of Automotive Systems-on-Chip. - Paolo Bernardi 002; Giorgio Insinga; G. Paganini; Riccardo Cantoro; P. Beer; M. Coppetta; N. Mautone; G. Carnevale; Pierre Scaramuzza; Rudolf Ullmann (ETS, 2022)

Recent Trends and Perspectives on Defect-Oriented Testing. - Paolo Bernardi 002; Riccardo Cantoro; Anthony Coyette; W. Dobbeleare; Moritz Fieback; Andrea Floridia; G. Gielenk; Jhon Gomez; Michelangelo Grosso; Andrea Guerriero; Iacopo Guglielminetti; Said Hamdioui; et al. (IOLTS, 2022)

Runtime Test Solution for Adaptive Aging Compensation and Fail Operational Safety mode. - Vincent Huard; Francois Jacquet; Souhir Mhira; Lionel Jure; Olivier Montfort; Mathieu Louvat; L. Zaia; F. Bertrand; E. Acacia; O. Caffin; H. Belhadj; O. Durand; et al. (IRPS, 2022)

A novel SEU injection setup for Automotive SoC. - Giusy Iaria; Tommaso Foscale; Paolo Bernardi 002; Luca Presicce; Matteo Sonza Reorda; Davide Appello; Vincenzo Tancorre; Roberto Ugioli (ISIE, 2022)

An innovative Strategy to Quickly Grade Functional Test Programs. - Francesco Angione; Paolo Bernardi 002; Andrea Calabrese; Lorenzo Cardone; A. Niccoletti; Davide Piumatti; Stefano Quer; Davide Appello; Vincenzo Tancorre; Roberto Ugioli (ITC, 2022)

A novel Pattern Selection Algorithm to reduce the Test Cost of large Automotive Systems-on-Chip. - Giusy Iaria; Francesco Angione; Paolo Bernardi 002; Matteo Sonza Reorda; Davide Appello; Giuseppe Garozzo; Vincenzo Tancorre (LATS, 2022)

Parallel Multithread Analysis of Extremely Large Simulation Traces. - Davide Appello; Paolo Bernardi 002; Andrea Calabrese; Giorgio Pollaccia; Stefano Quer; Vincenzo Tancorre; Roberto Ugioli (IEEE Access, 2022)

Collecting diagnostic information through dichotomic search from Logic BIST of failing in-field automotive SoCs with delay faults. - Paolo Bernardi 002; Gabriele Filipponi; Matteo Sonza Reorda; Davide Appello; Claudia Bertani; Vincenzo Tancorre (DDECS, 2023)

About the Correlation between Logical Identified Faulty Gates and their Layout Characteristics. - Paolo Bernardi 002; Lorenzo Cardone; Giusy Iaria; Davide Appello; Giuseppe Garozzo; Vincenzo Tancorre (IOLTS, 2023)

On the integration and hardening of Software Test Libraries in Real-Time Operating Systems. - Francesco Angione; Paolo Bernardi 002; Riccardo Cantoro; Nicola Di Gruttola Giardino; Davide Piumatti; Matteo Sonza Reorda; Davide Appello; Vincenzo Tancorre (LATS, 2023)

Low cost external serial interface watchdog for SoCs and FPGAs automatic characterization tests. - Paolo Bernardi 002; Gabriele Filipponi; Tommaso Foscale; Giorgio Insinga (LATS, 2023)

A Novel Approach to Extract Embedded Memory Design Parameter Through Irradiation Test. - Paolo Bernardi 002; Giorgio Insinga; Nima Kolahimahmoudi (VLSI-SoC, 2023)

A guided debugger-based fault injection methodology for assessing functional test programs. - Francesco Angione; Paolo Bernardi 002; Nicola Di Gruttola Giardino; Davide Appello; Claudia Bertani; Vincenzo Tancorre (VTS, 2023)

A Toolchain to Quantify Burn-In Stress Effectiveness on Large Automotive System-on-Chips. - Francesco Angione; Davide Appello; Paolo Bernardi 002; Andrea Calabrese; Stefano Quer; Matteo Sonza Reorda; Vincenzo Tancorre; Roberto Ugioli (IEEE Access, 2023)

A Low-Cost Burn-In Tester Architecture to Supply Effective Electrical Stress. - Francesco Angione; Davide Appello; Paolo Bernardi 002; Claudia Bertani; Giovambattista Gallo; Stefano Littardi; Giorgio Pollaccia; Walter Ruggeri; Matteo Sonza Reorda; Vincenzo Tancorre; Roberto Ugioli (IEEE Trans. Computers, 2023)

A Flexible FPGA-Based Test Equipment for Enabling Out-of-Production Manufacturing Test Flow of Digital Systems. - Nicola Di Gruttola Giardino; Francesco Angione; Paolo Bernardi 002; Tommaso Foscale; Claudia Bertani; Vincenzo Tancorre (DFT, 2024)

A 6-bit Low-Area Hybrid ADC Design For System-on-Chip Measurements. - Nima Kolahimahmoudi; Giorgio Insinga; Stefano Roggi; Josef Niederl; Paolo Bernardi 002 (DTTIS, 2024)

Optimizing System-Level Test Program Generation via Genetic Programming. - Denis Schwachhofer; Francesco Angione; Steffen Becker 001; Stefan Wagner 001; Matthias Sauer 002; Paolo Bernardi 002; Ilia Polian (ETS, 2024)

Exploring trade-offs in multi-site wafer testing. - Paolo Bernardi 002; Lorenzo Cardone; Tommaso Foscale (LATS, 2024)

Late Breaking Results: A Data Compaction Strategy for Extensive Test Flows of Memories Embedded in Automotive SoCs. - Paolo Bernardi 002; B. Borio; Giorgio Insinga; B. Mendicino; M. Battilana; M. Coppetta; N. Mautone; Pierre Scaramuzza; F. Tengler; Rudolf Ullmann (DATE, 2025)

HW/SW Co-Design of a Reliable Deep Space System Exploiting Application-Profiled RAM Scrubbing. - Nicola Di Gruttola Giardino; Paolo Bernardi 002; Sabrina Corpino; Fabrizio Stesina (DFT, 2025)

European Test Symposium Teams: an Anniversary Snapshot. - Maksim Jenihhin; Jaan Raik; Artur Jutman; Natalia Cherezova; Raimund Ubar; Liviu Miclea; Szilárd Enyedi; Iulia Stefan; Ovidiu Stan; Cosmina Corches; Zebo Peng; Petru Eles; et al. (ETS, 2025)

Exploiting weak detections for optimizing pattern generation in Defect-Oriented Cell-Aware ATPG. - Alessandro Ciullo; Stephan Eggersglüß; Daniel Tille; Andreas Glowatz; Giusy Iaria; Paolo Bernardi 002 (ITC-Asia, 2025)

System-Level Test techniques for Automotive SoCs. - Francesco Angione; Paolo Bernardi 002; Riccardo Cantoro (ITC, 2025)

Leveraging ATE to Optimize System-Level-Test for Multicore Automotive SoCs. - Francesco Angione; Paolo Bernardi 002; Claudia Bertani; Lorenzo Bertetto; Lorenzo Cardone; Nicola Di Gruttola Giardino; Stefano Quer; Vincenzo Tancorre (LATS, 2025)

Enhancing Logic Diagnosis of Field Returns Through Logic BIST in Automotive SoCs. - Paolo Bernardi 002; Gabriele Filipponi; Giusy Iaria; Claudia Bertani; Vincenzo Tancorre (LATS, 2025)

Special Session: Trustworthy Hardware-AI at the Cloud. - Francesco Angione; Paolo Bernardi 002; Alberto Bosio; Harish Dattatraya Dixit; Salvatore Pappalardo; Annachiara Ruospo; Ernesto Sánchez 001; Arani Sinha; Vittorio Turco (VTS, 2025)

A System-Level Test Methodology for Communication Peripherals in System-on-Chips. - Francesco Angione; Paolo Bernardi 002; Nicola Di Gruttola Giardino; Gabriele Filipponi; Claudia Bertani; Vincenzo Tancorre (IEEE Trans. Computers, 2025)

A Comprehensive Scan Test Cost Model to Optimize the Production of Very Large SoCs. - Giusy Iaria; Paolo Bernardi 002; Claudia Bertani; Lorenzo Cardone; Giuseppe Garozzo; Vincenzo Tancorre (IEEE Trans. Computers, 2025)

Automatic Generation of System-Level Test for Un-Core Logic of Large Automotive SoC. - Francesco Angione; Paolo Bernardi 002; Giusy Iaria; Claudia Bertani; Vincenzo Tancorre (IEEE Trans. Computers, 2025)

A Novel Indirect Methodology Based on Execution Traces for Grading Functional Test Programs. - Francesco Angione; Paolo Bernardi 002; Andrea Calabrese; Lorenzo Cardone; Stefano Quer; Claudia Bertani; Vincenzo Tancorre (IEEE Trans. Computers, 2025)

A Versatile Strategy for Comprehensive Data Collection and Retention in Embedded SoC Memories. - Paolo Bernardi 002; Giorgio Insinga; M. Battilana; P. Beer; Giambattista Carnevale; Matteo Coppetta; Nellina Mautone; Alberto Repele; Pierre Scaramuzza; Rudolf Ullmann (ACM Trans. Embed. Comput. Syst., 2026)

Netlist-Independent Functional Stress Pattern Generation Strategy for AI HW Accelerators Embedded into SoCs. - Gabriele Filipponi; Denis Schwachhofer; Francesco Angione; Claudia Bertani; Simone Corbellini; Nicola Di Gruttola Giardino; Giuseppe Garozzo; Giorgio Insinga; Vincenzo Tancorre; Paolo Bernardi 002 (IEEE Trans. Computers, 2026)