Networks on Chips: A Synthesis Perspective. - Federico Angiolini; Paolo Meloni; Luca Benini; Salvatore Carta; Luigi Raffo (PARCO, 2005)

Contrasting a NoC and a traditional interconnect fabric with layout awareness. - Federico Angiolini; Paolo Meloni; Salvatore Carta; Luca Benini; Luigi Raffo (DATE, 2006)

Designing application-specific networks on chips with floorplan information. - Srinivasan Murali; Paolo Meloni; Federico Angiolini; David Atienza; Salvatore Carta; Luca Benini; Giovanni De Micheli; Luigi Raffo (ICCAD, 2006)

Area and Power Modeling Methodologies for Networks-on-Chip. - Paolo Meloni; Salvatore Carta; Roberto Argiolas; Luigi Raffo; Federico Angiolini (Nano-Net, 2006)

Routing Aware Switch Hardware Customization for Networks on Chips. - Paolo Meloni; Srinivasan Murali; Salvatore Carta; Massimo Camplani; Luigi Raffo; Giovanni De Micheli (Nano-Net, 2006)

Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips. - Srinivasan Murali; Paolo Meloni; Federico Angiolini; David Atienza; Salvatore Carta; Luca Benini; Giovanni De Micheli; Luigi Raffo (VLSI-SoC, 2006)

Designing Routing and Message-Dependent Deadlock Free Networks on Chips. - Srinivasan Murali; Paolo Meloni; Federico Angiolini; David Atienza; Salvatore Carta; Luca Benini; Giovanni De Micheli; Luigi Raffo (VLSI-SoC (Selected Papers), 2006)

On the impact of serialization on the cache performances in Network-on-Chip based MPSoCs. - Paolo Meloni; Giovanni Busonera; Salvatore Carta; Luigi Raffo (DSD, 2007)

NoC Design and Implementation in 65nm Technology. - Antonio Pullini; Federico Angiolini; Paolo Meloni; David Atienza; Srinivasan Murali; Luigi Raffo; Giovanni De Micheli; Luca Benini (NOCS, 2007)

A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs. - Federico Angiolini; Paolo Meloni; Salvatore Carta; Luigi Raffo; Luca Benini (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. - Srinivasan Murali; David Atienza; Paolo Meloni; Salvatore Carta; Luca Benini; Giovanni De Micheli; Luigi Raffo (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Area and Power Modeling for Networks-on-Chip with Layout Awareness. - Paolo Meloni; Igor Loi; Federico Angiolini; Salvatore Carta; Massimo Barbaro; Luigi Raffo; Luca Benini (VLSI Design, 2007)

Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures. - Simone Secchi; Paolo Meloni; Luigi Raffo (ISPASS, 2010)

Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper. - Paolo Meloni; Simone Secchi; Luigi Raffo (VLSI-SoC, 2010)

An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures. - Paolo Meloni; Simone Secchi; Luigi Raffo (IEEE Embed. Syst. Lett., 2010)

Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not? - Emanuele Cannella; Lorenzo Di Gregorio; Leandro Fiorin; Menno Lindwer; Paolo Meloni; Olaf Neugebauer; Andy D. Pimentel (ESTIMedia, 2011)

Exploiting binary translation for fast ASIP design space exploration on FPGAs. - Sebastiano Pomata; Paolo Meloni; Giuseppe Tuveri; Luigi Raffo; Menno Lindwer (DATE, 2012)

ASAM: Automatic Architecture Synthesis and Application Mapping. - Lech Józwiak; Menno Lindwer; Rosilde Corvino; Paolo Meloni; Laura Micconi; Jan Madsen; Erkan Diken; Deepak Gangadharan; Roel Jordans; Sebastiano Pomata; Paul Pop; Giuseppe Tuveri; et al. (DSD, 2012)

System Adaptivity and Fault-Tolerance in NoC-based MPSoCs: The MADNESS Project Approach. - Paolo Meloni; Giuseppe Tuveri; Luigi Raffo; Emanuele Cannella; Todor P. Stefanov; Onur Derin; Leandro Fiorin; Mariagiovanna Sami (DSD, 2012)

Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems. - Paolo Meloni; Sebastiano Pomata; Luigi Raffo; Roberta Piscitelli; Andy D. Pimentel (ICSAMOS, 2012)

Towards Self-Adaptive KPN Applications on NoC-Based MPSoCs. - Onur Derin; Prasanth Kuncheerath Ramankutty; Paolo Meloni; Emanuele Cannella (Adv. Softw. Eng., 2012)

Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks. - Emanuele Cannella; Onur Derin; Paolo Meloni; Giuseppe Tuveri; Todor P. Stefanov (VLSI Design, 2012)

Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper. - Paolo Meloni; Sebastiano Pomata; Giuseppe Tuveri; Simone Secchi; Luigi Raffo; Menno Lindwer (VLSI Design, 2012)

Welcome to the 2013 conference on design and architectures for signal and image processing (DASIP) in Cagliari, Italy. - Paolo Meloni; Christophe Jégo (DASIP, 2013)

A runtime adaptive H.264 video-decoding MPSoC platform. - Giuseppe Tuveri; Simone Secchi; Paolo Meloni; Luigi Raffo; Emanuele Cannella (DASIP, 2013)

A Low Overhead Self-adaptation Technique for KPN Applications on NoC-based MPSoCs. - Onur Derin; Prasanth Kuncheerath Ramankutty; Paolo Meloni; Giuseppe Tuveri (PECCS, 2013)

A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project. - Onur Derin; Emanuele Cannella; Giuseppe Tuveri; Paolo Meloni; Todor P. Stefanov; Leandro Fiorin; Luigi Raffo; Mariagiovanna Sami (Microprocess. Microsystems, 2013)

ASAM: Automatic architecture synthesis and application mapping. - Lech Józwiak; Menno Lindwer; Rosilde Corvino; Paolo Meloni; Laura Micconi; Jan Madsen; Erkan Diken; Deepak Gangadharan; Roel Jordans; Sebastiano Pomata; Paul Pop; Giuseppe Tuveri; et al. (Microprocess. Microsystems, 2013)

A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks. - Paolo Meloni; Giuseppe Tuveri; Luigi Raffo; Igor Loi; Francesco Conti 001 (MES, 2014)

Online process transformation for polyhedral process networks in shared-memory MPSoCs. - Paolo Meloni; Giuseppe Tuveri; Luigi Raffo; Igor Loi; Francesco Conti 001 (MECO, 2014)

A Custom MPSoC Architecture With Integrated Power Management for Real-Time Neural Signal Decoding. - Nicola Carta; Paolo Meloni; Giuseppe Tuveri; Danilo Pani; Luigi Raffo (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)

The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms. - Francesca Palumbo; Nicola Carta; Danilo Pani; Paolo Meloni; Luigi Raffo (J. Real Time Image Process., 2014)

Exploring custom heterogeneous MPSoCs for real-time neural signal decoding. - Paolo Meloni; Giuseppe Tuveri; Danilo Pani; Luigi Raffo; Francesca Palumbo (DASIP, 2015)

Power modelling for saving strategies in coarse grained reconfigurable systems. - Tiziana Fanni; Carlo Sau; Paolo Meloni; Luigi Raffo; Francesca Palumbo (ReConFig, 2015)

Reconfigurable coprocessors synthesis in the MPEG-RVC domain. - Carlo Sau; Luca Fanni; Paolo Meloni; Luigi Raffo; Francesca Palumbo (ReConFig, 2015)

Power and clock gating modelling in coarse grained reconfigurable systems. - Tiziana Fanni; Carlo Sau; Paolo Meloni; Luigi Raffo; Francesca Palumbo (Conf. Computing Frontiers, 2016)

Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA. - Paolo Meloni; Gianfranco Deriu; Francesco Conti 001; Igor Loi; Luigi Raffo; Luca Benini (Conf. Computing Frontiers, 2016)

Demo: Reconfigurable Platform Composer Tool. - Carlo Sau; Tiziana Fanni; Paolo Meloni; Luigi Raffo; Maxime Pelcat; Francesca Palumbo (DASIP, 2016)

A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC. - Paolo Meloni; Gianfranco Deriu; Francesco Conti 001; Igor Loi; Luigi Raffo; Luca Benini (ReConFig, 2016)

Dataflow-Based Design of Coarse-Grained Reconfigurable Platforms. - Francesca Palumbo; Carlo Sau; Tiziana Fanni; Paolo Meloni; Luigi Raffo (SiPS, 2016)

Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures. - Francesca Palumbo; Tiziana Fanni; Carlo Sau; Paolo Meloni; Luigi Raffo (J. Electr. Comput. Eng., 2016)

MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation. - Paolo Meloni; Francesca Palumbo; Claudio Rubattu; Giuseppe Tuveri; Danilo Pani; Luigi Raffo (Microprocess. Microsystems, 2016)

On-the-fly adaptivity for process networks over shared-memory platforms. - Giuseppe Tuveri; Paolo Meloni; Francesca Palumbo; Giovanni Pietro Seu; Igor Loi; Francesco Conti 001; Luigi Raffo (Microprocess. Microsystems, 2016)

Automated Design Flow for Multi-Functional Dataflow-Based Platforms. - Carlo Sau; Paolo Meloni; Luigi Raffo; Francesca Palumbo; Endri Bezati; Simone Casale Brunet; Marco Mattavelli (J. Signal Process. Syst., 2016)

Feasibility Study of Real-Time Spiking Neural Network Simulations on a Swarm Intelligence Based Digital Architecture. - Francesca Palumbo; Carlo Sau; Danilo Pani; Paolo Meloni; Luigi Raffo (IPDPS Workshops, 2017)

On-FPGA Real-Time Processing of Biological Signals From High-Density MEAs: a Design Space Exploration. - Giovanni Pietro Seu; Gian Nicola Angotzi; Giuseppe Tuveri; Luigi Raffo; Luca Berdondini; Alessandro Maccione; Paolo Meloni (IPDPS Workshops, 2017)

Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing. - Carlo Sau; Francesca Palumbo; Maxime Pelcat; Julien Heulot; Erwan Nogues; Daniel Ménard; Paolo Meloni; Luigi Raffo (IEEE Embed. Syst. Lett., 2017)

Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs. - Paolo Meloni; Claudio Rubattu; Giuseppe Tuveri; Danilo Pani; Luigi Raffo; Francesca Palumbo (J. Syst. Archit., 2017)

Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy. - Francesca Palumbo; Tiziana Fanni; Carlo Sau; Paolo Meloni (J. Signal Process. Syst., 2017)

ALOHA: an architectural-aware framework for deep learning at the edge. - Paolo Meloni; Daniela Loi; Gianfranco Deriu; Andy D. Pimentel; Dolly Sapra; Bernhard Moser 001; Natalia Shepeleva; Francesco Conti 001; Luca Benini; Oscar Ripolles; David Solans; Maura Pintor; et al. (INTESA@ESWEEK, 2018)

Architecture-aware design and implementation of CNN algorithms for embedded inference: the ALOHA project. - Paolo Meloni; Daniela Loi; Gianfranco Deriu; Andy D. Pimentel; Dolly Sapra; Maura Pintor; Battista Biggio; Oscar Ripolles; David Solans; Francesco Conti 001; Luca Benini; Todor P. Stefanov; et al. (ICM, 2018)

Exploiting All Programmable SoCs in Neural Signal Analysis: A Closed-Loop Control for Large-Scale CMOS Multielectrode Arrays. - Giovanni Pietro Seu; Gian Nicola Angotzi; Fabio Boi; Luigi Raffo; Luca Berdondini; Paolo Meloni (IEEE Trans. Biomed. Circuits Syst., 2018)

NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs. - Paolo Meloni; Alessandro Capotondi; Gianfranco Deriu; Michele Brian; Francesco Conti 001; Davide Rossi; Luigi Raffo; Luca Benini (ACM Trans. Reconfigurable Technol. Syst., 2018)

Optimization and deployment of CNNs at the edge: the ALOHA experience. - Paolo Meloni; Daniela Loi; Paola Busia; Gianfranco Deriu; Andy D. Pimentel; Dolly Sapra; Todor P. Stefanov; Svetlana Minakova; Francesco Conti 001; Luca Benini; Maura Pintor; Battista Biggio; et al. (CF, 2019)

A runtime-adaptive cognitive IoT node for healthcare monitoring. - Matteo Antonio Scrugli; Daniela Loi; Luigi Raffo; Paolo Meloni (CF, 2019)

Flexible Acceleration of Convolutions on FPGAs: NEURAghe 2.0. - Marco Carreras; Gianfranco Deriu; Paolo Meloni (CPS Summer School, PhD Workshop, 2019)

Runtime-Adaptive Cognitive IoT Nodes. - Matteo Antonio Scrugli; Daniela Loi; Luigi Raffo; Paolo Meloni (CPS Summer School, PhD Workshop, 2019)

CNN hardware acceleration on a low-power and low-cost APSoC. - Paolo Meloni; Antonio Garufi; Gianfranco Deriu; Marco Carreras; Daniela Loi (DASIP, 2019)

A Closed-Loop System Processing High-Density Electrical Recordings and Visual Stimuli to Study Retinal Circuits Properties. - Sara Zaher; Davide Lonardoni; Fabio Boi; Giovanni Pietro Seu; Gian Nicola Angotzi; Paolo Meloni; Luca Berdondini (NER, 2019)

Biosensing IoT Platform for Water Management in Vineyards. - Silvia Loddo; M. Soccol; A. Perra; M. Ucchesu; Paolo Meloni; Massimo Barbaro; Mauro Lo Cascio; C. Sirca (ISCAS, 2020)

ZyON: Enabling Spike Sorting on APSoC-Based Signal Processors for High-Density Microelectrode Arrays. - Gianluca Leone; Luigi Raffo; Paolo Meloni (IEEE Access, 2020)

Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge. - Paolo Meloni; Daniela Loi; Gianfranco Deriu; Marco Carreras; Francesco Conti 001; Alessandro Capotondi; Davide Rossi (IEEE Embed. Syst. Lett., 2020)

Optimizing Temporal Convolutional Network Inference on FPGA-Based Accelerators. - Marco Carreras; Gianfranco Deriu; Luigi Raffo; Luca Benini; Paolo Meloni (IEEE J. Emerg. Sel. Topics Circuits Syst., 2020)

Task-Specific Automation in Deep Learning Processes. - Georg Buchgeher; Gerald Czech; Adriano Souza Ribeiro; Werner Kloihofer; Paolo Meloni; Paola Busia; Gianfranco Deriu; Maura Pintor; Battista Biggio; Cristina Chesta; Luca Rinelli; David Solans; et al. (DEXA Workshops, 2021)

ALOHA: A Unified Platform-Aware Evaluation Method for CNNs Execution on Heterogeneous Systems at the Edge. - Paola Busia; Svetlana Minakova; Todor P. Stefanov; Luigi Raffo; Paolo Meloni (IEEE Access, 2021)

Proceedings of the DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021). - Frank Hannig; Paolo Meloni; Matteo Spallanzani; Matthias Ziegler 001 (CoRR, 2021)

EEGformer: Transformer-Based Epilepsy Detection on Raw EEG Traces for Low-Channel-Count Wearable Continuous Monitoring Devices. - Paola Busia; Andrea Cossettini; Thorir Mar Ingolfsson; Simone Benatti; Alessio Burrello; Moritz Scherer 001; Matteo Antonio Scrugli; Paolo Meloni; Luca Benini (BioCAS, 2022)

Dynamic Pruning for Parsimonious CNN Inference on Embedded Systems. - Paola Busia; Ilias Theodorakopoulos; Vasileios K. Pothos; Nikos Fragoulis; Paolo Meloni (DASIP, 2022)

An Adaptable Cognitive Microcontroller Node for Fitness Activity Recognition. - Matteo Antonio Scrugli; Bojan Blazica; Paolo Meloni (DASIP, 2022)

Integration of Energy Storage Systems within Modular Multilevel Converters for Medium-Voltage Distribution Networks. - Paolo Meloni; Alessandro Serpi (IECON, 2022)

Target-Aware Neural Architecture Search and Deployment for Keyword Spotting. - Paola Busia; Gianfranco Deriu; Luca Rinelli; Cristina Chesta; Luigi Raffo; Paolo Meloni (IEEE Access, 2022)

A Bandwidth-Efficient Emulator of Biologically-Relevant Spiking Neural Networks on FPGA. - Gianluca Leone; Luigi Raffo; Paolo Meloni (IEEE Access, 2022)

An Adaptive Cognitive Sensor Node for ECG Monitoring in the Internet of Medical Things. - Matteo Antonio Scrugli; Daniela Loi; Luigi Raffo; Paolo Meloni (IEEE Access, 2022)

On-FPGA Spiking Neural Networks for Multi-variable End-to-End Neural Decoding. - Gianluca Leone; Luca Martis; Luigi Raffo; Paolo Meloni (ARC, 2023)

Spiking Neural Networks for Integrated Reach-to-Grasp Decoding on FPGAs. - Gianluca Leone; Luca Martis; Luigi Raffo; Paolo Meloni (BioCAS, 2023)

On-FPGA Spiking Neural Networks for End-to-End Neural Decoding. - Gianluca Leone; Luigi Raffo; Paolo Meloni (IEEE Access, 2023)

A Microcontroller-Based Platform for Cognitive Tracking of Sensorimotor Training. - Matteo Antonio Scrugli; Bojan Blazica; Luigi Raffo; Paolo Meloni (IEEE Access, 2023)

An Automated Design Flow for Adaptive Neural Network Hardware Accelerators. - Francesco Ratto; Ángela Porras Máinez; Carlo Sau; Paolo Meloni; Gianfranco Deriu; Stefano Delucchi; Massimo Massa; Luigi Raffo; Francesca Palumbo (J. Signal Process. Syst., 2023)

Exploiting FPGAs and Spiking Neural Networks at the Micro-Edge: The EdgeAI Approach. - Paolo Meloni; Paola Busia; Gianluca Leone; Luca Martis; Matteo Antonio Scrugli (ARC, 2024)

Spiking Neural Networks for Near-Sensor Processing: An Open-Hardware Experience. - Luca Martis; Gianluca Leone; Luigi Raffo; Paolo Meloni (CPS Summer School, PhD Workshop, 2024)

sEMG-Based Gesture Recognition with Spiking Neural Networks on Low-Power FPGA. - Matteo Antonio Scrugli; Gianluca Leone; Paola Busia; Paolo Meloni (DASIP, 2024)

On-FPGA Spiking Neural Networks for Integrated Near-Sensor ECG Analysis. - Matteo Antonio Scrugli; Paola Busia; Gianluca Leone; Paolo Meloni (DATE, 2024)

Design of an AI-driven Architecture with Cobots for Digital Transformation to Enhance Quality Control in the Food Industry. - Paola Busia; Claudio Marche; Paolo Meloni; Diego Reforgiato Recupero (UMAP (Adjunct Publication), 2024)

A Noisy Beat is Worth 16 Words: a Tiny Transformer for Low-Power Arrhythmia Classification on Microcontrollers. - Paola Busia; Matteo Antonio Scrugli; Victor Jean-Baptiste Jung; Luca Benini; Paolo Meloni (CoRR, 2024)

Reducing False Alarms in Wearable Seizure Detection With EEGformer: A Compact Transformer Model for MCUs. - Paola Busia; Andrea Cossettini; Thorir Mar Ingolfsson; Simone Benatti; Alessio Burrello; Victor J. B. Jung; Moritz Scherer 001; Matteo Antonio Scrugli; Adriano Bernini; Pauline Ducouret; Philippe Ryvlin; Paolo Meloni; et al. (IEEE Trans. Biomed. Circuits Syst., 2024)

SYNtzulA: Open-Source Hardware for Energy-Efficient Spiking Neural Network Inference. - Luca Martis; Gianluca Leone; Luigi Raffo; Paolo Meloni (CF (Companion), 2025)

Endoscopy Image Classification for Wireless Capsules with CNNs on Microcontroller-Based Platforms. - Paola Busia; Andrea Pinna 001; Paolo Meloni (DASIP, 2025)

Enabling SNN-Based Near-MEA Neural Decoding with Channel Selection: An Open-HW Approach. - Gianluca Leone; Luca Martis; Luigi Raffo; Paolo Meloni (DATE, 2025)

A Tiny Transformer for Low-Power Arrhythmia Classification on Microcontrollers. - Paola Busia; Matteo Antonio Scrugli; Victor Jean-Baptiste Jung; Luca Benini; Paolo Meloni (IEEE Trans. Biomed. Circuits Syst., 2025)

Real-Time sEMG Processing With Spiking Neural Networks on a Low-Power 5K-LUT FPGA. - Matteo Antonio Scrugli; Gianluca Leone; Paola Busia; Luigi Raffo; Paolo Meloni (IEEE Trans. Biomed. Circuits Syst., 2025)

SYNtzulu: A Tiny RISC-V-Controlled SNN Processor for Real-Time Sensor Data Analysis on Low-Power FPGAs. - Gianluca Leone; Matteo Antonio Scrugli; Lorenzo Badas; Luca Martis; Luigi Raffo; Paolo Meloni (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)