Fast cone-of-influence computation and estimation in problems with multiple properties. - Carmelo Loiacono; Marco Palena; Paolo Pasini; Denis Patti; Stefano Quer; Stefano Ricossa; Danilo Vendraminetto; Jason Baumgartner (DATE, 2013)

Tightening BDD-based approximate reachability with SAT-based clause generalization∗. - Gianpiero Cabodi; Paolo Pasini; Stefano Quer; Danilo Vendraminetto (DATE, 2014)

Interpolation with Guided Refinement: Revisiting incrementality in SAT-based unbounded model checking. - Gianpiero Cabodi; Marco Palena; Paolo Pasini (FMCAD, 2014)

Hardware Model Checking Competition 2014: An Analysis and Comparison of Solvers and Benchmarks. - Gianpiero Cabodi; Carmelo Loiacono; Marco Palena; Paolo Pasini; Denis Patti; Stefano Quer; Danilo Vendraminetto; Armin Biere; Keijo Heljanko (J. Satisf. Boolean Model. Comput., 2014)

Test Time Minimization in Reconfigurable Scan Networks. - Riccardo Cantoro; Marco Palena; Paolo Pasini; Matteo Sonza Reorda (ATS, 2016)

A 7/2-Approximation Algorithm for the Maximum Duo-Preservation String Mapping Problem. - Nicolas Boria; Gianpiero Cabodi; Paolo Camurati; Marco Palena; Paolo Pasini; Stefano Quer (CPM, 2016)

Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening. - Gianpiero Cabodi; Paolo Camurati; Marco Palena; Paolo Pasini; Danilo Vendraminetto (FMCAD, 2016)

A Greedy Approach to Answer Reachability Queries on DAGs. - Nicolas Boria; Gianpiero Cabodi; Paolo Camurati; Marco Palena; Paolo Pasini; Stefano Quer (CoRR, 2016)

Interpolation-Based Learning as a Mean to Speed-Up Bounded Model Checking (Short Paper). - Gianpiero Cabodi; Paolo Camurati; Marco Palena; Paolo Pasini; Danilo Vendraminetto (SEFM, 2017)

SAT solver management strategies in IC3: an experimental approach. - Gianpiero Cabodi; Paolo Camurati; Alan Mishchenko; Marco Palena; Paolo Pasini (Formal Methods Syst. Des., 2017)

Improving bit-level model checking algorithms for scalability through circuit-based reasoning. - Paolo Pasini (2017)

To split or to group: from divide-and-conquer to sub-task sharing for verifying multiple properties in model checking. - Gianpiero Cabodi; Paolo Camurati; Carmelo Loiacono; Marco Palena; Paolo Pasini; Denis Patti; Stefano Quer (Int. J. Softw. Tools Technol. Transf., 2018)

Test of Reconfigurable Modules in Scan Networks. - Riccardo Cantoro; Farrokh Ghani Zadegan; Marco Palena; Paolo Pasini; Erik Larsson; Matteo Sonza Reorda (IEEE Trans. Computers, 2018)

Logic Synthesis for Interpolant Circuit Compaction. - Gianpiero Cabodi; Paolo Camurati; Marco Palena; Paolo Pasini; Danilo Vendraminetto (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Reducing Interpolant Circuit Size Through SAT-Based Weakening. - Gianpiero Cabodi; Paolo Camurati; Marco Palena; Paolo Pasini; Danilo Vendraminetto (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Optimizing Binary Decision Diagrams for Interpretable Machine Learning Classification. - Gianpiero Cabodi; Paolo E. Camurati; Alexey Ignatiev; João Marques-Silva 001; Marco Palena; Paolo Pasini (DATE, 2021)

Interpolation with guided refinement: revisiting incrementality in SAT-based unbounded model checking. - Gianpiero Cabodi; Paolo E. Camurati; Marco Palena; Paolo Pasini (Formal Methods Syst. Des., 2022)

Improving Bounded Model Checking Exploiting Interpolation-Based Learning and Strengthening. - Gianpiero Cabodi; Paolo E. Camurati; Marco Palena; Paolo Pasini (IEEE Access, 2024)

Hardware Model Checking Algorithms and Techniques. - Gianpiero Cabodi; Paolo E. Camurati; Marco Palena; Paolo Pasini (Algorithms, 2024)

Optimizing Binary Decision Diagrams for Interpretable Machine Learning Classification. - Gianpiero Cabodi; Paolo E. Camurati; João Marques-Silva 001; Marco Palena; Paolo Pasini (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A Theorem Prover Based Approach for SAT-Based Model Checking Certification. - Giulia Sindoni; Paolo Pasini; Gianpiero Cabodi; Paolo E. Camurati; Alberto Griggio; Marco Palena; Marco Roveri; Stefano Tonetta (CADE, 2025)

Low-Power Subgraph Isomorphism at the Edge Using FPGAs. - Roberto Bosio; Giovanni Brignone; Teodoro Urso; Mihai T. Lazarescu; Luciano Lavagno; Paolo Pasini (IEEE Access, 2025)

NN2FPGA: Optimizing CNN Inference on FPGAs With Binary Integer Programming. - Roberto Bosio; Filippo Minnella; Teodoro Urso; Mario R. Casu; Luciano Lavagno; Mihai T. Lazarescu; Paolo Pasini (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)