Exact GPS simulation with logarithmic complexity, and its application to an optimally fair scheduler. - Paolo Valente (SIGCOMM, 2004)

Extending WF^2 Q+ to Support a Dynamic Traffic Mix. - Paolo Valente (AAA-IDEA, 2005)

Design and Testing of Scalable Web-Based Systems with Performance Constraints. - Mauro Andreolini; Michele Colajanni; Paolo Valente (FIRB-Perf, 2005)

An Upper Bound to the Lateness of Soft Real-Time Tasks Scheduled by EDF on Multiprocessors. - Paolo Valente; Giuseppe Lipari (RTSS, 2005)

Scheduling algorithms for quality of service provisioning. - Paolo Valente (2005)

Exact GPS simulation and optimal fair scheduling with logarithmic complexity. - Paolo Valente (IEEE/ACM Trans. Netw., 2007)

An STDMA-based framework for QoS provisioning in wireless mesh networks. - Mauro Leoncini; Paolo Santi; Paolo Valente (MASS, 2008)

High Throughput Disk Scheduling with Fair Bandwidth Distribution. - Paolo Valente; Fabio Checconi (IEEE Trans. Computers, 2010)

Improving application responsiveness with the BFQ disk I/O scheduler. - Paolo Valente; Mauro Andreolini (SYSTOR, 2012)

Direct vs 2-Stage Approaches to Structured Motif Finding. - Maria Federico; Mauro Leoncini; Manuela Montangero; Paolo Valente (Algorithms Mol. Biol., 2012)

A Modular Architecture for QoS Provisioning over Wireless Links. - Maurizio Casoni; Alessandro Paganelli; Paolo Valente (AINA Workshops, 2013)

Providing Near-Optimal Fair-Queueing Guarantees at Round-Robin Amortized Cost. - Paolo Valente (ICCCN, 2013)

QFQ: Efficient Packet Scheduling With Tight Guarantees. - Fabio Checconi; Luigi Rizzo; Paolo Valente (IEEE/ACM Trans. Netw., 2013)

A low-latency and high-throughput scheduler for emergency and wireless networks. - Maurizio Casoni; Carlo Augusto Grazia; Paolo Valente (ICC Workshops, 2014)

TEMPEST: Test environment for performance evaluation of the scheduling of packets. - Carlo Augusto Grazia; Maurizio Casoni; Paolo Valente (WiMob, 2014)

Reducing the execution time of fair-queueing packet schedulers. - Paolo Valente (Comput. Commun., 2014)

TEMPEST: a new Test EnvironMent for Performance Evaluation of the Scheduling of packeTs. - Maurizio Casoni; Carlo Augusto Grazia; Paolo Valente (Simul. Model. Pract. Theory, 2014)

Integrating Linux and the real-time ERIKA OS through the Xen hypervisor. - Arianna Avanzini; Paolo Valente; Dario Faggioli; Paolo Gai (SIES, 2015)

On service guarantees of fair-queueing schedulers in real systems. - Luigi Rizzo; Paolo Valente (Comput. Commun., 2015)

A Survey on Shared I/O Management in Virtualized Environments under Real Time Constraints. - Ignacio Sanudo Olmedo; Roberto Cavicchioli; Nicola Capodieci; Paolo Valente; Marko Bertogna (EWiLi, 2016)

Using a lag-balance property to tighten tardiness bounds for global EDF. - Paolo Valente (Real Time Syst., 2016)

SiGAMMA: server based integrated GPU arbitration mechanism for memory accesses. - Nicola Capodieci; Roberto Cavicchioli; Paolo Valente; Marko Bertogna (RTNS, 2017)

A branch-and-bound algorithm to compute a tighter bound to tardiness for preemptive global EDF scheduler. - Mauro Leoncini; Manuela Montangero; Paolo Valente (RTNS, 2017)

PSPAT: Software packet scheduling at hardware speed. - Luigi Rizzo; Paolo Valente; Giuseppe Lettieri; Vincenzo Maffione (Comput. Commun., 2018)

Achieving a high throughput and a low latency through a modular packet scheduler. - Maurizio Casoni; Carlo Augusto Grazia; Paolo Valente (Int. J. Commun. Networks Distributed Syst., 2018)

A survey on shared disk I/O management in virtualized environments under real time constraints. - Ignacio Sanudo Olmedo; Roberto Cavicchioli; Nicola Capodieci; Paolo Valente; Marko Bertogna (SIGBED Rev., 2018)

Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems. - Tomasz Kloda; Marco Solieri; Renato Mancuso 001; Nicola Capodieci; Paolo Valente; Marko Bertogna (RTAS, 2019)

A parallel branch-and-bound algorithm to compute a tighter tardiness bound for preemptive global EDF. - Mauro Leoncini; Manuela Montangero; Paolo Valente (Real Time Syst., 2019)

Managing Human-driven and Autonomous Vehicles at Smart Intersections. - Giacomo Cabri; Manuela Montangero; Filippo Muzzini; Paolo Valente (ICHMS, 2020)

Evaluating Controlled Memory Request Injection to Counter PREM Memory Underutilization. - Roberto Cavicchioli; Nicola Capodieci; Marco Solieri; Marko Bertogna; Paolo Valente; Andrea Marongiu (JSSPP, 2020)

Novel Methodology for Assessing Chip-Package Interaction Effects onChip Performance. - Armen Kteyan; Jun-Ho Choy; Valeriy Sukharev; Massimo Bertoletti; Carmelo Maiorca; Rossana Zadra; Massimo Inzaghi; Gabriele Gattere; Giancarlo Zinco; Paolo Valente; Roberto Bardelli; Alessandro Valerio; et al. (ISPD, 2022)

Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-based Heterogeneous SoCs. - Gianluca Brilli; Giacomo Valente; Alessandro Capotondi; Paolo Burgio; T. Di Masciov; Paolo Valente; Andrea Marongiu (DAC, 2023)

The Importance of Worst-Case Memory Contention Analysis for Heterogeneous SoCs. - Lorenzo Carletti; Gianluca Brilli; Alessandro Capotondi; Paolo Valente; Andrea Marongiu (CoRR, 2023)

Evaluating Controlled Memory Request Injection for Efficient Bandwidth Utilization and Predictable Execution in Heterogeneous SoCs. - Gianluca Brilli; Roberto Cavicchioli; Marco Solieri; Paolo Valente; Andrea Marongiu (ACM Trans. Embed. Comput. Syst., 2023)

HMB: Scheduling PREM-Like Real-Time Tasks at High Memory Bandwidth (Invited Paper). - Mohammadhassan Gholami Derouei; Paolo Valente; Marco Solieri; Andrea Marongiu (NG-RES@HiPEAC, 2024)

Taking a closer look at memory interference effects in commercial-off-the-shelf multicore SoCs. - Lorenzo Carletti; Andrea Serafini; Gianluca Brilli; Alessandro Capotondi; Alessandro Biasci; Paolo Valente; Andrea Marongiu (J. Syst. Archit., 2025)

Synchronous VS asynchronous reconfiguration of Memory Bandwidth Management Schemes: A comparative analysis. - Andrea Serafini; Alessandro Biasci; Bruno Morelli; Paolo Valente; Andrea Marongiu (J. Syst. Archit., 2025)

Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-Based Heterogeneous SoCs. - Giacomo Valente; Gianluca Brilli; Tania Di Mascio; Alessandro Capotondi; Paolo Burgio; Paolo Valente; Andrea Marongiu (IEEE Trans. Parallel Distributed Syst., 2025)