Testing using a minimal number of instructions. - Parag K. Lala (Microprocess. Microsystems, 1981)

Redefinable crossassembler for horizontally microprogrammable processors. - Nigel F. Scholes; Gary Morgan; Parag K. Lala (Microprocess. Microsystems, 1984)

Fault tolerance and self-checking techniques in microprocessor-based system design. - Parag K. Lala (Softw. Microsystems, 1985)

On Built-In Testing of VLSI Chips. - Parag K. Lala (ITC, 1986)

A Concurrent Testing Strategy for PLAs. - Dali L. Tao; Carlos R. P. Hartmann; Parag K. Lala (ITC, 1986)

An efficient class of unidirectional error detecting/correcting codes. - Dali L. Tao; Carlos R. P. Hartmann; Parag K. Lala (IEEE Trans. Computers, 1988)

A MOS implementation of totally self-checking checker for the 1-out-of-3 code. - Dali L. Tao; Parag K. Lala; Carlos R. P. Hartmann (IEEE J. Solid State Circuits, 1988)

A scheme for designing fault-tolerant microprogrammed processors using bit-slice chips. - Parag K. Lala (Microprocessing and Microprogramming, 1990)

An approach for designing self-checking logic using residue codes. - Parag K. Lala; Fadi Y. Busaba; K. C. Yarlagadda (VTS, 1991)

A Note on t-EC/d-UED Codes. - Dali L. Tao; Carlos R. P. Hartmann; Parag K. Lala (IEEE Trans. Computers, 1991)

A new technique for totally self-checking CMOS circuit design for stuck-on and stuck-off faults. - Manjit S. Cheema; Parag K. Lala (VTS, 1992)

A concurrent checking scheme for single and multibit errors in logic circuits. - B. Kolla; Parag K. Lala; K. C. Yarlagadda (VTS, 1992)

Fault Diagnosis in Analog Circuits Using Element Modulation. - Alvernon Walker; Winser E. Alexander; Parag K. Lala (IEEE Des. Test Comput., 1992)

A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay. - Dali L. Tao; Carlos R. P. Hartmann; Parag K. Lala (IEEE Trans. Computers, 1992)

Totally self-checking CMOS circuit design for breaks and stuck-on faults. - Manjit S. Cheema; Parag K. Lala (IEEE J. Solid State Circuits, 1992)

Input and output encoding techniques for on-line error detection in combinational logic circuits. - Fadi Y. Busaba; Parag K. Lala (VTS, 1993)

Self-checking combinational circuit design for single and unidirectional multibit error. - Fadi Y. Busaba; Parag K. Lala (J. Electron. Test., 1994)

Partially Strongly Fault Secure and Partially Strongly Code Disjoint I-out-of-3 Code Checker. - J. Q. Wang; Parag K. Lala (IEEE Trans. Computers, 1994)

Techniques for Self-Checking Combinational Logic Synthesis. - Fadi Busaba; Parag K. Lala (VLSI Design, 1994)

An Approach for Self-Checking Realization of Interacting Finite State Machines. - Fadi Busaba; Parag K. Lala (VLSI Design, 1994)

A graph coloring based approach for self-checking logic circuit design. - Fadi Y. Busaba; Parag K. Lala (Asian Test Symposium, 1995)

A unified approach for off-line and on-line testing of VLSI systems. - Parag K. Lala; S. Yang; Fadi Busaba (DFT, 1996)

Modular implementation of efficient self-checking checkers for the Berger code. - D. A. Pierce; Parag K. Lala (J. Electron. Test., 1996)

Multiple Fault Detection in Fan-Out Free Circuits Using Minimal Single Fault Test Set. - K. Lai; Parag K. Lala (IEEE Trans. Computers, 1996)

An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring. - Alvernon Walker; Algernon P. Henry; Parag K. Lala (DFT, 1997)

On-Line Testable Logic Desgin for FPGA Implementation. - Alfred L. Burress; Parag K. Lala (ITC, 1997)

On Self-Checking Design of CMOS Circuits for Multiple Faults. - Fadi Busaba; Parag K. Lala; Alvernon Walker (VLSI Design, 1998)

Guest Editorial. - Parag K. Lala (VLSI Design, 1998)

A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs. - Parag K. Lala; Anup Singh; Alvernon Walker (DFT, 1999)

Self-Checking Logic Design for LUT-Based FPGAs. - Parag K. Lala; Alfred L. Burress (FPGA, 1999)

A technique for designing self-checking logic for FPGAs. - Parag K. Lala; Alfred L. Burress (ISCAS (1), 1999)

An On-Line Reconfigurable FPGA Architecture. - Parag K. Lala; Alvernon Walker (DFT, 2000)

Fault Analysis of the Multiple Valued Logic Using Spectral Method. - Jong O. Kim; Parag K. Lala; Young Gun Kim; Heung-Soo Kim (ISMVL, 2000)

A Transition Based BIST Approach for Passive Analog Circuits. - Alvernon Walker; Parag K. Lala (ISQED, 2000)

A Unified Scheme for Designing Testable State Machines. - Parag K. Lala; Alvernon Walker (Asian Test Symposium, 2001)

On-Line Error Detectable Carry-Free Adder Design. - Parag K. Lala; Alvernon Walker (DFT, 2001)

An Approach for Designing On-Line Testable State Machines. - Parag K. Lala; Mark G. Karpovsky (IOLTW, 2001)

A Fine Grain Configurable Logic Block for Self-checking FPGAs. - Parag K. Lala; Alvernon Walker (VLSI Design, 2001)

On Biologically-Inspired Design of Fault-Tolerant Digital Systems. - Parag K. Lala; K. K. Bondali (DELTA, 2002)

Human Immune System Inspired Architecture for Self-Healing Digital Systems. - Parag K. Lala; B. Kiran Kumar (ISQED, 2002)

On-line Error Detection in a Carry-free Adder. - Whitney J. Townsend; Mitchell A. Thornton; Parag K. Lala (IWLS, 2002)

A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory Systems. - Parag K. Lala (DFT, 2003)

An FPGA architecture with built-in error correction capability. - Parag K. Lala; B. Kiran Kumar (FPGA, 2003)

Fault Injection in Digital Logic Circuits at the VHDL Level. - S. R. Seward; Parag K. Lala (IOLTS, 2003)

On-Line Error Detecting Constant Delay Adder. - Whitney J. Townsend; Jacob A. Abraham; Parag K. Lala (IOLTS, 2003)

On-line Detection of Faults in Carry-Select Adders. - B. Kiran Kumar; Parag K. Lala (ITC, 2003)

Fault Injection for Verifying Testability at the VHDL Level. - S. R. Seward; Parag K. Lala (ITC, 2003)

An Architecture for Self-Healing Digital Systems. - Parag K. Lala; B. Kiran Kumar (J. Electron. Test., 2003)

Self-checking logic design for FPGA implementation. - Parag K. Lala; Alfred L. Burress (IEEE Trans. Instrum. Meas., 2003)

A Novel Approach for On-line Testable Reversible Logic Circuit Desig. - Dilip P. Vasudevan; Parag K. Lala; James Patrick Parkerson (Asian Test Symposium, 2004)

A New Reversible Logic Gate and its Applications. - Dilip P. Vasudevan; Parag K. Lala (ESA/VLSI, 2004)

Online Testable Reversible Logic Circuit Design using NAND Blocks. - Dilip P. Vasudevan; Parag K. Lala; James Patrick Parkerson (DFT, 2004)

Logic implementation using a reversible gate. - Dilip P. Vasudevan; James Patrick Parkerson; Parag K. Lala (Circuits, Signals, and Systems, 2004)

On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits. - Jia Di; Parag K. Lala; Dilip P. Vasudevan (DFT, 2005)

A Technique for Modular Design of Self-Checking Carry-Select Adder. - Dilip P. Vasudevan; Parag K. Lala (DFT, 2005)

A Technique for Designing Totally Self-Checking Domino Logic Circuits. - C. K. Tang; Parag K. Lala; James Patrick Parkerson (ISQED, 2005)

CMOS Realization of Online Testable Reversible Logic Gates. - Dilip P. Vasudevan; Parag K. Lala; James Patrick Parkerson (ISVLSI, 2005)

On self-healing digital system design. - Parag K. Lala; B. Kiran Kumar; James Patrick Parkerson (Microelectron. J., 2006)

Reversible-logic design with online testability. - Dilip P. Vasudevan; Parag K. Lala; Jia Di; James Patrick Parkerson (IEEE Trans. Instrum. Meas., 2006)

Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems. - Jia Di; Parag K. Lala (J. Electron. Test., 2007)

Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding. - Dilip P. Vasudevan; Parag K. Lala; James Patrick Parkerson (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

On FPGA Design with Self-checking and Fault Tolerance Capability. - Parag K. Lala (ERSA, 2008)

An Introduction to Logic Circuit Testing - Parag K. Lala (Morgan & Claypool Publishers, 2008)

A Quantum Key Distribution Protocol. - Parag K. Lala (Security and Management, 2010)

An Approach for Implementing State Machines with Online Testability. - Parag K. Lala; Adam Mathews; James Patrick Parkerson (VLSI Design, 2010)