Loop Filter Design Considerations for Noise-Shaping in SAR ADCs. - Anamika Sharma; Luv Pandey; Paras Garg; Rajesh Zele (ISCAS, 2024)

A Novel 2.7 pJ/bit, Low Supply, Power Efficient, Wide-Range 2.5-6 Gb/s Transmitter for 4-Channel High-Speed Serial Transmit Port (HSSTP) in 28nm FD-SOI Technology. - Sameer Vashishtha; Prashant Kumar Singh; Mohd. Rizvi; Paras Garg (ISCAS, 2024)

Three-Level Output Side Gate Driver for 1 V Thin-Gate-Oxide NMOSFET Switch in a SIDO Converter. - Abhijit Keshri; Pramit Banerjee; Gautam Dey Kanungo; Kallol Chatterjee; Paras Garg; Santanu Kapat; Debashis Mandal (ISCAS, 2025)