Automatic stability checking for large linear analog integrated circuits. - Parijat Mukherjee; G. Peter Fang; Rod Burt; Peng Li 001 (DAC, 2011)

Efficient Identification of Unstable Loops in Large Linear Analog Integrated Circuits. - Parijat Mukherjee; G. Peter Fang; Rod Burt; Peng Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Approximate property checking of mixed-signal circuits. - Parijat Mukherjee; Chirayu S. Amin; Peng Li 001 (DAC, 2014)

Leveraging pre-silicon data to diagnose out-of-specification failures in mixed-signal circuits. - Parijat Mukherjee; Peng Li 001 (DAC, 2014)

Using Presilicon Knowledge to Excite Nonlinear Failure Modes in Large Mixed-Signal Circuits. - Parijat Mukherjee; Peng Li 001 (IEEE Des. Test, 2016)

The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Yishuang Lin; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Steven M. Burns; Ramesh Harjani; Jiang Hu; Parijat Mukherjee; Soner Yaldiz; et al. (ICCAD, 2020)

Learning from Experience: Applying ML to Analog Circuit Design. - Kishor Kunal; Tonmoy Dhar; Yaguang Li; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Ramesh Harjani; Jiang Hu; Parijat Mukherjee; Sachin S. Sapatnekar (ISPD, 2020)

Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs. - Yuting Cao; Parijat Mukherjee; Mahesh Ketkar; Jin Yang 006; Hao Zheng 001 (ISQED, 2020)

Common-Centroid Layouts for Analog Circuits: Advantages and Limitations. - Arvind K. Sharma; Meghna Madhusudan; Steven M. Burns; Parijat Mukherjee; Soner Yaldiz; Ramesh Harjani; Sachin S. Sapatnekar (DATE, 2021)

Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits. - Arvind K. Sharma; Meghna Madhusudan; Steven M. Burns; Soner Yaldiz; Parijat Mukherjee; Ramesh Harjani; Sachin S. Sapatnekar (ICCAD, 2021)

Model Synthesis for Communication Traces of System Designs. - Hao Zheng 001; Md Rubel Ahmed; Parijat Mukherjee; Mahesh C. Ketkar; Jin Yang 006 (ICCD, 2021)

Machine Learning Techniques in Analog Layout Automation. - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Yishuang Lin; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Steven M. Burns; Ramesh Harjani; Jiang Hu; Parijat Mukherjee; Soner Yaldiz; et al. (ISPD, 2021)

Mining Message Flows from System-on-Chip Execution Traces. - Md Rubel Ahmed; Hao Zheng 001; Parijat Mukherjee; Mahesh C. Ketkar; Jin Yang 006 (ISQED, 2021)

A Comparative Study of Specification Mining Methods for SoC Communication Traces. - Md Rubel Ahmed; Hao Zheng 001; Parijat Mukherjee; Mahesh C. Ketkar; Jin Yang 006 (ISVLSI, 2021)

Model Synthesis for Communication Traces of System-on-Chip Designs. - Hao Zheng 001; Md Rubel Ahmed; Parijat Mukherjee; Mahesh C. Ketkar; Jin Yang 006 (CoRR, 2021)

ALIGN: A System for Automating Analog Layout. - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Ramesh Harjani; Jiang Hu; Desmond A. Kirkpatrick; Parijat Mukherjee; et al. (IEEE Des. Test, 2021)

Mining Patterns From Concurrent Execution Traces. - Md Rubel Ahmed; Hao Zheng 001; Parijat Mukherjee; Mahesh C. Ketkar; Jin Yang 006 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients. - Arvind K. Sharma; Meghna Madhusudan; Steven M. Burns; Soner Yaldiz; Parijat Mukherjee; Ramesh Harjani; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)