A reconfigurable linear feedback shift register (LFSR) for the Bluetooth system. - Paris Kitsos; Nicolas Sklavos 001; Nikolaos D. Zervas; Odysseas G. Koufopavlou (ICECS, 2001)

An efficient implementation of the digital signature algorithm. - Paris Kitsos; Nicolas Sklavos 001; Odysseas G. Koufopavlou (ICECS, 2002)

VLSI implementation of password (PIN) authentication unit. - Nicolas Sklavos 001; Paris Kitsos; Odysseas G. Koufopavlou (ICECS, 2002)

Euclidean algorithm VLSI implementations. - Nicolas Sklavos 001; Kyriakos Papadomanolakis; Paris Kitsos; Odysseas G. Koufopavlou (ICECS, 2002)

Hardware implementation of the SAFER+ encryption algorithm for the Bluetooth system. - Paris Kitsos; Nicolas Sklavos 001; Odysseas G. Koufopavlou (ISCAS (4), 2002)

Random number generator architecture and VLSI implementation. - Nicolas Sklavos 001; Paris Kitsos; Kyriakos Papadomanolakis; Odysseas G. Koufopavlou (ISCAS (4), 2002)

VLSI implementations of the triple-DES block cipher. - Paris Kitsos; S. Goudevenos; Odysseas G. Koufopavlou (ICECS, 2003)

An reconfigurable multiplier in GF(2m) for elliptic curve cryptosystem. - Paris Kitsos; George Theodoridis; Odysseas G. Koufopavlou (ICECS, 2003)

An efficient reconfigurable multiplier architecture for Galois field GF(2m). - Paris Kitsos; George Theodoridis; Odysseas G. Koufopavlou (Microelectron. J., 2003)

Hardware Implementation of Bluetooth Security. - Paraskevas Kitsos; Nicolas Sklavos 001; Kyriakos Papadomanolakis; Odysseas G. Koufopavlou (IEEE Pervasive Comput., 2003)

Comparison of the hardware architectures and FPGA implementations of stream ciphers. - Michalis D. Galanis; Paris Kitsos; Giorgos Kostopoulos; Nicolas Sklavos 001; Odysseas G. Koufopavlou; Costas E. Goutis (ICECS, 2004)

High performance cryptographic engine PANAMA: hardware implementation. - Georgios N. Selimis; Paris Kitsos; Odysseas G. Koufopavlou (ICECS, 2004)

High-speed hardware implementations of the KASUMI block cipher. - Paris Kitsos; Michalis D. Galanis; Odysseas G. Koufopavlou (ISCAS (2), 2004)

Whirlpool hash function: architecture and VLSI implementation. - Paris Kitsos; Odysseas G. Koufopavlou (ISCAS (2), 2004)

64-bit Block ciphers: hardware implementations and comparison analysis. - Paris Kitsos; Nicolas Sklavos 001; Michalis D. Galanis; Odysseas G. Koufopavlou (Comput. Electr. Eng., 2004)

Configurable Hardware Implementations of Bulk Encryption Units for Wireless Communications. - Paris Kitsos; Odysseas G. Koufopavlou (Int. Arab J. Inf. Technol., 2004)

Open Mobile Alliance (OMA) Security Layer: Architecture, Implementation and Performance Evaluation of the Integrity Unit. - Nicolas Sklavos 001; Paris Kitsos; Epaminondas Alexopoulos; Odysseas G. Koufopavlou (New Gener. Comput., 2004)

Efficient architecture and hardware implementation of the Whirlpool hash function. - Paris Kitsos; Odysseas G. Koufopavlou (IEEE Trans. Consumer Electron., 2004)

A RAM-based FPGA implementation of the 64-bit MISTY1 block cipher. - Paris Kitsos; Michalis D. Galanis; Odysseas G. Koufopavlou (ISCAS (5), 2005)

Cryptography: Circuits and Systems Approach. - Odysseas G. Koufopavlou; George N. Selimis; Nicolas Sklavos 001; Paris Kitsos (PATMOS, 2005)

On the Hardware Implementation of the MICKEY-128 Stream Cipher. - Paris Kitsos (IACR Cryptol. ePrint Arch., 2005)

Comparison of the Hardware Implementation of Stream Ciphers. - Michalis D. Galanis; Paris Kitsos; Giorgos Kostopoulos; Nicolas Sklavos 001; Constantinos E. Goutis (Int. Arab J. Inf. Technol., 2005)

An Fpga Implementation of the Gprs Encryption Algorithm 3 (gea3). - Paris Kitsos; Michalis D. Galanis; Odysseas G. Koufopavlou (J. Circuits Syst. Comput., 2005)

Architectures and FPGA Implementations of the 64-Bit MISTY1 Block Cipher. - Paris Kitsos; Michalis D. Galanis; Odysseas G. Koufopavlou (J. Circuits Syst. Comput., 2006)

Design, Architecture and Performance Evaluation of the Wireless Transport Layer Security. - Nicolas Sklavos 001; Paris Kitsos; K. Papadopoulos; Odysseas G. Koufopavlou (J. Supercomput., 2006)

A high-speed hardware implementation of the Hermes8-128 stream cipher. - Paris Kitsos; Ulrich Kaiser (ECCTD, 2007)

A System-on-Chip Design of the RadioGatún Hash Function. - Paris Kitsos; Bhanu Prasad 001 (HPCNCS, 2007)

An FPGA-based implementation of the Pomaranch stream cipher. - Paris Kitsos; Odysseas G. Koufopavlou (MobiMedia, 2007)

Guest Editors' Introduction to the Special Issue on Security of Computers and Networks. - Paris Kitsos; Nicolas Sklavos 001 (Comput. Electr. Eng., 2007)

UMTS security: system architecture and hardware implementation. - Paris Kitsos; Nicolas Sklavos 001; Odysseas G. Koufopavlou (Wirel. Commun. Mob. Comput., 2007)

A Hardware Implementation of CURUPIRA Block Cipher for Wireless Sensors. - Paris Kitsos; George N. Selimis; Odysseas G. Koufopavlou; Athanassios N. Skodras (DSD, 2008)

Secure multimedia communication. - Shiguo Lian; Yan Zhang 002; Jong Hyuk Park 001; Paris Kitsos (Secur. Commun. Networks, 2008)

The Self-synchronizing Stream Cipher Moustique. - Joan Daemen; Paris Kitsos (The eSTREAM Finalists, 2008)

Editorial: Special Issue on "Information Security and Data Protection in Future Generation Communication and Networking". - Jong Hyuk Park 001; Han-Chieh Chao; Whai-En Chen; Paris Kitsos (Wirel. Pers. Commun., 2009)

Low Power FPGA Implementations of 256-bit Luffa Hash Function. - Paris Kitsos; Nicolas Sklavos 001; Athanassios N. Skodras (DSD, 2010)

On the hardware implementation efficiency of SHA-3 candidates. - Paris Kitsos; Nicolas Sklavos 001 (ICECS, 2010)

BLAKE HASH Function Family on FPGA: From the Fastest to the Smallest. - Nicolas Sklavos 001; Paris Kitsos (ISVLSI, 2010)

An FPGA Implementation of the ZUC Stream Cipher. - Paris Kitsos; Nicolas Sklavos 001; Athanassios N. Skodras (DSD, 2011)

Low Power FPGA Implementations of JH and Fugue Hash Functions. - George Provelengios; Nikolaos S. Voros; Paris Kitsos (DSD, 2011)

An FPGA implementation and performance evaluation of the seed block cipher. - Paris Kitsos; Athanassios N. Skodras (DSP, 2011)

Snmp for Ethernet Networks SETH: A Network Benchmark Toolkit for Managing Routers Statistical Information. - Sotirios Kontogiannis; Alexandros Karakos; George Kokkonis; Paraskevas Kitsos (Panhellenic Conference on Informatics, 2011)

Bit-serial and digit-serial GF(2m)Montgomery multipliers using linear feedback shift registers. - Miguel Morales-Sandoval; Claudia Feregrino Uribe; Paraskevas Kitsos (IET Comput. Digit. Tech., 2011)

FPGA-based Design Approaches of Keccak Hash Function. - George Provelengios; Paris Kitsos; Nicolas Sklavos 001; Christos Koulamas (DSD, 2012)

VLSI Design and Implementation of Homophonic Security System. - Nicolas Sklavos 001; Paris Kitsos; Odysseas G. Koufopavlou (ISVLSI, 2012)

Architectural Optimizations & Hardware Implementations of WLANs Encryption Standard. - Nicolas Sklavos 001; Paris Kitsos (NTMS, 2012)

A comparative study of hardware architectures for lightweight block ciphers. - Paris Kitsos; Nicolas Sklavos 001; Maria Parousi; Athanassios N. Skodras (Comput. Electr. Eng., 2012)

An Efficient FPGA-Based Architecture of Skein for Simple Hashing and MAC Function. - Filippos Pirpilidis; Paris Kitsos; Nicolas Sklavos 001 (DSD, 2013)

A high speed FPGA implementation of the 2D DCT for Ultra High Definition video coding. - Paris Kitsos; Nikolaos S. Voros; Tasos Dagiuklas; Athanassios N. Skodras (DSP, 2013)

Area/performance trade-off analysis of an FPGA digit-serial GF(2m)GF(2m) Montgomery multiplier based on LFSR. - Miguel Morales-Sandoval; Claudia Feregrino Uribe; Paraskevas Kitsos; René Cumplido (Comput. Electr. Eng., 2013)

FPGA-based performance analysis of stream ciphers ZUC, Snow3g, Grain V1, Mickey V2, Trivium and E0. - Paris Kitsos; Nicolas Sklavos 001; George Provelengios; Athanassios N. Skodras (Microprocess. Microsystems, 2013)

Editorial of special issue: Digital System Safety and Security. - Hana Kubátová; Paris Kitsos (Microprocess. Microsystems, 2013)

FPGA Trojan Detection Using Length-Optimized Ring Oscillators. - Paris Kitsos; Artemios G. Voyiatzis (DSD, 2014)

Cipher Text Stealing integrated in implementations of IEEE P1619 for shared storage media. - Athanasios Kakarountas; Epameinontas Hatzidimitriou; Paris Kitsos (ISCCSP, 2014)

Towards a hardware Trojan detection methodology. - Paris Kitsos; Artemios G. Voyiatzis (MECO, 2014)

Guest Editorial: Smart Grid Communications Systems. - Seong-Lyun Kim; Paris Kitsos; Maziar M. Nekovee; F. Richard Yu; Yan Zhang 002 (IEEE Syst. J., 2014)

A Comparison of TERO and RO Timing Sensitivity for Hardware Trojan Detection Applications. - Paris Kitsos; Artemios G. Voyiatzis (DSD, 2015)

Exciting FPGA cryptographic Trojans using combinatorial testing. - Paris Kitsos; Dimitris E. Simos; Jose Torres-Jimenez; Artemios G. Voyiatzis (ISSRE, 2015)

A compact design of SEED block cipher. - Filippos Pirpilidis; Paris Kitsos; Athanasios Kakarountas (MECO, 2015)

Comparing design approaches for elliptic curve point multiplication over GF(2k) with polynomial basis representation. - Apostolos P. Fournaris; Ioannis Zafeirakis; Paris Kitsos; Odysseas G. Koufopavlou (Microprocess. Microsystems, 2015)

Efficient triggering of Trojan hardware logic. - Artemios G. Voyiatzis; Kyriakos G. Stefanidis; Paris Kitsos (DDECS, 2016)

TERO-Based Detection of Hardware Trojans on FPGA Implementation of the AES Algorithm. - Paris Kitsos; Kyriakos Stefanidis; Artemios G. Voyiatzis (DSD, 2016)

An FPGA design for the Two-Band Fast Discrete Hartley Transform. - Lambros Pyrgas; Paris Kitsos; Athanassios N. Skodras (ISSPIT, 2016)

An Efficient Reconfigurable Ring Oscillator for Hardware Trojan Detection. - Filippos Pirpilidis; Artemios G. Voyiatzis; Lambros Pyrgas; Paris Kitsos (PCI, 2016)

Introduction to Special Issue on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE). - Lilian Bossuet; Giorgio Di Natale; Paris Kitsos (Microprocess. Microsystems, 2016)

Run-Time Effect by Inserting Hardware Trojans, in Combinational Circuits. - Fotios Kounelis; Nicolas Sklavos 001; Paris Kitsos (DSD, 2017)

Thermal Sensor Based Hardware Trojan Detection in FPGAs. - Lampros Pyrgas; Filippos Pirpilidis; Aliki Panayiotarou; Paris Kitsos (DSD, 2017)

MICPRO DSD 2015 special issue. - João Canas Ferreira; Paris Kitsos (Microprocess. Microsystems, 2017)

On the effects of ring oscillator length and hardware Trojan size on an FPGA-based implementation of AES. - Filippos Pirpilidis; Kyriakos G. Stefanidis; Artemios G. Voyiatzis; Paris Kitsos (Microprocess. Microsystems, 2017)

A Hybrid FPGA Trojan Detection Technique Based-on Combinatorial Testing and On-chip Sensing. - Lampros Pyrgas; Paris Kitsos (ARC, 2018)

An FPGA Hardware Trojan Detection Approach Based on Multiple Parameter Analysis. - Apostolos P. Fournaris; Lampros Pyrgas; Paris Kitsos (DSD, 2018)

A 4-bit Architecture of SEED Block Cipher for IoT Applications. - Filippos Pirpilidis; Lampros Pyrgas; Paris Kitsos (ICECS, 2018)

Compact FPGA architectures for the two-band fast discrete Hartley transform. - Lampros Pyrgas; Paris Kitsos; Athanassios Skodras (Microprocess. Microsystems, 2018)

DSD-i1: A Mixed Functionality Development Board Geared Towards Digital Systems Design Education. - Anastasios Fanariotis; Theofanis Orphanoudakis; Vasilios Fotopoulos; Paris Kitsos (DSD, 2019)

A Very Compact Architecture of CLEFIA Block Cipher for Secure IoT Systems. - Lampros Pyrgas; Paris Kitsos (DSD, 2019)

An 8-bit Compact Architecture of Lesamnta-LW Hash Function for Constrained Devices. - Lampros Pyrgas; Paris Kitsos (ICECS, 2019)

An efficient multi-parameter approach for FPGA hardware Trojan detection. - Apostolos P. Fournaris; Lampros Pyrgas; Paris Kitsos (Microprocess. Microsystems, 2019)

Are ring oscillators without a combinatorial loop good enough for Hardware Trojan detection? - Lampros Pyrgas; Aliki Panagiotarou; Paris Kitsos (DSD, 2020)

8-bit serialised architecture of SEED block cipher for constrained devices. - Filippos Pirpilidis; Lampros Pyrgas; Paris Kitsos (IET Circuits Devices Syst., 2020)

5G Security: FPGA Implementation of SNOW-V Stream Cipher. - Lampros Pyrgas; Paris Kitsos (DSD, 2021)

Importing Custom DNN Models on FPGAs. - Stavros Kalapothas; Georgios Flamis; Paris Kitsos (MECO, 2021)

Workflow on CNN utilization and inference in FPGA for embedded applications: 6th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM 2021). - Georgios Flamis; Stavros Kalapothas; Paris Kitsos (SEEDA-CECNSM, 2021)

Efficient majority logic magnitude comparator design. - Constantinos Efstathiou; Paris Kitsos (Microprocess. Microsystems, 2021)

FPGA-SoC Deployment of Complex Deep Neural Network for Magnitude and Phase Computations in Denoising of Speech Signal. - Georgios Flamis; Stavros Kalapothas; Paris Kitsos (VLSI-SoC, 2022)

Locating Hardware Trojans Using Combinatorial Testing for Cryptographic Circuits. - Ludwig Kampel; Paris Kitsos; Dimitris E. Simos (IEEE Access, 2022)

Efficient Edge-AI Application Deployment for FPGAs. - Stavros Kalapothas; Georgios Flamis; Paris Kitsos (Inf., 2022)

FPGA-Based Encryption System for Cloud Security. - Marios Papadopoulos; Paris Kitsos (DSD, 2023)

Summary of Locating Hardware Trojans using Combinatorial Testing for Cryptographic Circuits. - Ludwig Kampel; Paris Kitsos; Dimitris E. Simos (ICSTW, 2023)

On the modulo 2n+1 addition and subtraction for weighted operands. - Constantinos Efstathiou; Ioannis Kouretas; Paris Kitsos (Microprocess. Microsystems, 2023)

A Survey on RISC-V-Based Machine Learning Ecosystem. - Stavros Kalapothas; Manolis Galetakis; Georgios Flamis; Fotis C. Plessas; Paris Kitsos (Inf., 2023)

FPGA-Based Cloud Security Solutions for 5G Networks. - Marios Papadopoulos; Kostas Lampropoulos 002; Paris Kitsos (CSR, 2024)

SAND5G - Security Assessments for Networks and Services in 5G Networks. - Aimilia Bantouna; Kostas Lampropoulos 001; Omar Qaise; Andreas Stamoulis; Paris Kitsos; Kostas Poulios; Lampros Raptis; Christos Tranoris (DSD, 2024)

An Efficient Methodology for Real-Time Risk and Impact Assessment in 5G Networks. - Dionysia Varvarigou; Konstantinos Lampropoulos 001; Odysseas G. Koufopavlou; Spyros G. Denazis; Paris Kitsos (CSR, 2025)

Efficient Majority Logic Modulo 2n-1 Adder Design. - Constantinos Efstathiou; Ioannis Kouretas; Paris Kitsos (ISVLSI, 2025)

An FPGA Architecture of Extensible Authentication Protocol EAP- ΑΚA΄ for 5G Νetworks. - Marios Papadopoulos; Kostas Lampropoulos 002; Paris Kitsos (MECO, 2025)