A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing. - Parisa Mashreghi-Moghadam; Tarek Ould-Bachir; Yvon Savaria (ISCAS, 2022)

An Area-efficient Memory-based Architecture for P4-programmable Streaming Parsers in FPGAs. - Parisa Mashreghi-Moghadam; Tarek Ould-Bachir; Yvon Savaria (ISCAS, 2023)

PrismParser: A Framework for Implementing Efficient P4-Programmable Packet Parsers on FPGA. - Parisa Mashreghi-Moghadam; Tarek Ould-Bachir; Yvon Savaria (Future Internet, 2024)