REACT: Reactive Environment for Runtime Reconfiguration. - Dinesh Bhatia; PariVallal Kannan; Kuldeep S. Simha; Karthikeya M. Gajjala Purna (FPL, 1998)

NEBULA: A Partially and Dynamically Reconfigurable Architecture. - Dinesh Bhatia; Kuldeep S. Simha; PariVallal Kannan (FPL, 1999)

Tightly Integrated Placement and Routing for FPGAs. - PariVallal Kannan; Dinesh Bhatia (FPL, 2001)

fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits. - PariVallal Kannan; Shankar Balachandran; Dinesh Bhatia (FPL, 2001)

On metrics for comparing routability estimation methods for FPGAs. - PariVallal Kannan; Shankar Balachandran; Dinesh Bhatia (DAC, 2002)

Rapid and Reliable Routability Estimation for FPGAs. - PariVallal Kannan; Shankar Balachandran; Dinesh Bhatia (FPL, 2002)

On Routing Demand and Congestion Estimation for FPGAs. - Shankar Balachandran; PariVallal Kannan; Dinesh Bhatia (ASP-DAC/VLSI Design, 2002)

Interconnect Estimation for FPGAs under Timing Driven Domains. - PariVallal Kannan; Dinesh Bhatia (ICCD, 2003)

Estimating Pre-Placement FPGA Interconnection Requirements. - PariVallal Kannan; Dinesh Bhatia (VLSI Design, 2004)

On metrics for comparing interconnect estimation methods for FPGAs. - PariVallal Kannan; Shankar Balachandran; Dinesh Bhatia (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Interconnect estimation for FPGAs. - PariVallal Kannan; Dinesh Bhatia (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Performance driven routing for modern FPGAs. - PariVallal Kannan; Satish Sivaswamy (ICCAD, 2016)