A 3.6GHz, 16mW ΣΔ DAC for a 802.11n / 802.16e transmitter with 30dB digital power control in 90nm CMOS. - Parmoon Seddighrad; Ashoke Ravi; Masoud Sajadieh; Hasnain Lakdawala; Krishnamurthy Soumyanath (ESSCIRC, 2008)

A 2.5GHz, 6.9mW ΔΣ modulator with standard cell design in 45nm-LP CMOS using time-interleaving. - Paolo Madoglio; Ashoke Ravi; Luis Cuellar 001; Stefano Pellerano; Parmoon Seddighrad; Ismael Lomeli; Yorgos Palaskas (ESSCIRC, 2009)

A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving. - Paolo Madoglio; Ashoke Ravi; Luis Cuellar 001; Stefano Pellerano; Parmoon Seddighrad; Ismael Lomeli; Yorgos Palaskas (IEEE J. Solid State Circuits, 2010)

13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications. - Paolo Madoglio; Hongtao Xu; Kailash Chandrashekar; Luis Cuellar 001; Muhammad Faisal; Yee William Li; Hyung Seok Kim; Khoa Minh Nguyen; Yulin Tan; Brent R. Carlton; Vaibhav A. Vaidya; Yanjie Wang; et al. (ISSCC, 2017)

Transformer-Combining Digital PA with Efficiency Peaking at 0, -6, and -12 dB Backoff in 32nm CMOS. - Parmoon Seddighrad; Yorgos Palaskas; Hongtao Xu; Paolo Madoglio; Kailash Chandrashekar; David J. Allstot (ISCAS, 2020)