Designing DPA Resistant Circuits Using BDD Architecture and Bottom Pre-charge Logic. - Partha De; Kunal Banerjee 001; Chittaranjan A. Mandal; Debdeep Mukhopadhyay (DSD, 2013)

Circuits and Synthesis Mechanism for Hardware Design to Counter Power Analysis Attacks. - Partha De; Kunal Banerjee 001; Chittaranjan A. Mandal; Debdeep Mukhopadhyay (DSD, 2014)

A BDD based secure hardware design method to guard against power analysis attacks. - Partha De; Kunal Banerjee 001; Chittaranjan A. Mandal (VDAT, 2014)

Heuristics for 2-coverage multi point relay problem in wireless ad hoc and sensor networks. - Partha De; Kamil Saraç; Ramaswamy Chandrasekaran (WiOpt, 2016)

Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power and Timing Attacks. - Partha De; Chittaranjan Mandal 002; Udaya Parampalli (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Secure Path Balanced BDD-Based Pre-Charge Logic for Masking. - Partha De; Udaya Parampalli; Chittaranjan Mandal 002 (IEEE Trans. Circuits Syst., 2020)

Design of secure circuits resistant to side channel attacks for lightweight cryptography. - Partha De (2020)

ProvDP: Differential Privacy for System Provenance Dataset. - Kunal Mukherjee; Jonathan Yu; Partha De; Dinil Mon Divakaran (ACNS (3), 2025)