Parallelization of loops with exits on pipelined architectures. - Parthasarathy P. Tirumalai; Meng Lee; Michael S. Schlansker (SC, 1990)

Parallel Algorithms for Minimizing Multiple-Valued Programmable Logic Arrays. - Parthasarathy P. Tirumalai; Varadarajan G. Vadakkencherry (ISMVL, 1991)

Minimization Algorithms for Multiple-Valued Programmable Logic Arrays. - Parthasarathy P. Tirumalai; Jon T. Butler (IEEE Trans. Computers, 1991)

Parallelization of WHILE loops on pipelined architectures. - Parthasarathy P. Tirumalai; Meng Lee; Michael S. Schlansker (J. Supercomput., 1991)

Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. - Gerhard W. Dueck; Robert C. Earle; Parthasarathy P. Tirumalai; Jon T. Butler (ISMVL, 1992)

Code generation schema for modulo scheduled loops. - B. Ramakrishna Rau; Michael S. Schlansker; Parthasarathy P. Tirumalai (MICRO, 1992)

Register Allocation for Software Pipelined Loops. - B. Ramakrishna Rau; Meng Lee; Parthasarathy P. Tirumalai; Michael S. Schlansker (PLDI, 1992)