Synthesis strategies for sub-VT systems. - Pascal Andreas Meinerzhagen; Oskar Andersson; S. M. Yasser Sherazi; Andreas Peter Burg; Joachim Neves Rodrigues (ECCTD, 2011)

Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems. - Pascal Andreas Meinerzhagen; Onur Andiç; Jürg Treichler; Andreas Peter Burg (ACM Great Lakes Symposium on VLSI, 2011)

Benchmarking of Standard-Cell Based Memories in the Sub- VT Domain in 65-nm CMOS Technology. - Pascal Andreas Meinerzhagen; S. M. Yasser Sherazi; Andreas Peter Burg; Joachim Neves Rodrigues (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS. - Pascal Andreas Meinerzhagen; Oskar Andersson; Babak Mohammadi; S. M. Yasser Sherazi; Andreas Peter Burg; Joachim Neves Rodrigues (ESSCIRC, 2012)

Two-port low-power gain-cell storage array: Voltage scaling and retention time. - Rashid Iqbal; Pascal Andreas Meinerzhagen; Andreas Peter Burg (ISCAS, 2012)

Replica bit-line technique for embedded multilevel gain-cell DRAM. - Muhammad Umer Khalid; Pascal Meinerzhagen; Andreas Burg 001 (NEWCAS, 2012)

TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing. - Jeremy Constantin; Ahmed Yasir Dogan; Oskar Andersson; Pascal Andreas Meinerzhagen; Joachim Neves Rodrigues; David Atienza; Andreas Burg 001 (VLSI-SoC, 2012)

An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing. - Jeremy Constantin; Ahmed Yasir Dogan; Oskar Andersson; Pascal Andreas Meinerzhagen; Joachim Neves Rodrigues; David Atienza; Andreas Burg 001 (VLSI-SoC (Selected Papers), 2012)

FireBird: PowerPC e200 based SoC for high temperature operation. - Radisav Cojbasic; Omer Cogal; Pascal Andreas Meinerzhagen; Christian Senning; Conor Slater; Thomas Maeder; Andreas Burg 001; Yusuf Leblebici (CICC, 2013)

Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS. - Oskar Andersson; Babak Mohammadi; Pascal Meinerzhagen; Andreas Burg 001; Joachim Neves Rodrigues (ESSCIRC, 2013)

A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write. - Ibrahim Kazi; Pascal Meinerzhagen; Pierre-Emmanuel Gaillardon; Davide Sacchetto; Andreas Burg 001; Giovanni De Micheli (NEWCAS, 2013)

A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS. - Oskar Andersson; Babak Mohammadi; Pascal Andreas Meinerzhagen; Joachim Neves Rodrigues (ESSCIRC, 2014)

4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes. - Robert Giterman; Adam Teman; Pascal Andreas Meinerzhagen; Andreas Burg 001; Alexander Fish (ISCAS, 2014)

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design. - Ibrahim Kazi; Pascal Andreas Meinerzhagen; Pierre-Emmanuel Gaillardon; Davide Sacchetto; Yusuf Leblebici; Andreas Peter Burg; Giovanni De Micheli (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM. - Adam Teman; Pascal Andreas Meinerzhagen; Robert Giterman; Alexander Fish; Andreas Burg 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI. - Adam Teman; Davide Rossi; Pascal Andreas Meinerzhagen; Luca Benini; Andreas Peter Burg (ASP-DAC, 2015)

Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories. - Adam Teman; Georgios Karakonstantis; Robert Giterman; Pascal Andreas Meinerzhagen; Andreas Peter Burg (DATE, 2015)

Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder. - Pascal Andreas Meinerzhagen; Andrea Bonetti; Georgios Karakonstantis; Christoph Roth; Frank Giirkaynak; Andreas Peter Burg (ISCAS, 2015)

A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design. - Robert Giterman; Adam Teman; Pascal Meinerzhagen; Alexander Fish; Andreas Burg 001 (ISCAS, 2016)

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS. - Oskar Andersson; Babak Mohammadi; Pascal Meinerzhagen; Andreas Burg 001; Joachim Neves Rodrigues (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs. - Noa Edri; Pascal Meinerzhagen; Adam Teman; Andreas Burg 001; Alexander Fish (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement. - Adam Teman; Davide Rossi; Pascal Meinerzhagen; Luca Benini; Andreas Burg 001 (ACM Trans. Design Autom. Electr. Syst., 2016)

A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications. - Lior Atias; Adam Teman; Robert Giterman; Pascal Meinerzhagen; Alexander Fish (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications. - Robert Giterman; Adam Teman; Pascal Andreas Meinerzhagen; Lior Atias; Andreas Burg 001; Alexander Fish (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop. - Mahesh Nataraj; Alexandre Levisse; Bastien Giraud; Jean-Philippe Noël; Pascal Andreas Meinerzhagen; Jean-Michel Portal; Pierre-Emmanuel Gaillardon (ISCAS, 2017)

Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation. - Robert Giterman; Adam Teman; Pascal Meinerzhagen (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. - Pascal Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (ISSCC, 2018)

An All-Digital, VMAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop. - Suyoung Bang; Minki Cho; Pascal Meinerzhagen; Andres Malavasi; Muhammad M. Khellah; James W. Tschanz; Vivek De (ESSCIRC, 2019)

Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS. - Pascal Andreas Meinerzhagen; Sandip Kundu; Andres Malavasi; Trang Nguyen; Muhammad M. Khellah; James W. Tschanz; Vivek De (ESSCIRC, 2019)

An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{ text{MIN}}$ Optimization. - Pascal Andreas Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (IEEE J. Solid State Circuits, 2019)

Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization. - Srikanth Venkataraman; Pongpachara Limpisathian; Pascal Meinerzhagen; Suriyaprakash Natarajan; Eric Yang (ITC, 2020)

Automated Design For Yield Through Defect Tolerance. - Suriyaprakash Natarajan; Andres F. Malavasi; Pascal Andreas Meinerzhagen (VTS, 2020)

An All-Digital, $V_{ mathrm{MAX}}$ -Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop. - Suyoung Bang; Minki Cho; Pascal Andreas Meinerzhagen; Andres Malavasi; Muhammad M. Khellah; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2020)

A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS. - Charles Augustine; Pascal Meinerzhagen; Wootaek Lim; A. Veerabathini; M. Bright; K. Mojjada; Jim Tschanz; Muhammad M. Khellah; Vivek De (VLSI Technology and Circuits, 2023)

ISLPED 2023: International Symposium on Low-Power Electronics and Design. - Axel Jantsch; Swaroop Ghosh; Ümit Y. Ogras; Pascal Meinerzhagen (IEEE Des. Test, 2024)

Recap of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED'24). - Pascal Meinerzhagen; Kapil Dev; Jerald Yoo (IEEE Des. Test, 2025)