A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology. - Sandrine Bernardini; Jean-Michel Portal; Pascal Masson (DATE, 2004)

Characterization and Modeling of Gate-Induced-Drain-Leakage. - Fabien Gilibert; Denis Rideau; Alexandre Dray; François Agut; Michel Minondo; Andre Juge; Pascal Masson; Rachid Bouchakour (IEICE Trans. Electron., 2005)

MM11 based flash memory cell model including characterization procedure. - B. Saillet; Arnaud Régnier; Jean-Michel Portal; B. Delsuc; Romain Laffont; Pascal Masson; Rachid Bouchakour (ISCAS, 2006)

Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability. - Guillaume Just; Vincenzo Della Marca; Arnaud Régnier; Jean-Luc Ogier; Jérémy Postel-Pellerin; Jean-Michel Portal; Pascal Masson (J. Low Power Electron., 2012)

Investigation of the effects of constant voltage stress on thin SiO2 layers using dynamic measurement protocols. - Philippe Chiquet; Pascal Masson; Romain Laffont; Gilles Micolau; Jérémy Postel-Pellerin; Frédéric Lalande; Bernard Bouteille; Jean-Luc Ogier (Microelectron. Reliab., 2012)

Effects of 1064 nm laser on MOS capacitor. - R. Llido; Pascal Masson; Arnaud Régnier; Vincent Goubier; Gérald Haller; Vincent Pouget; Dean Lewis (Microelectron. Reliab., 2012)

Effect of ions presence in the SiOCH inter metal dielectric structure. - Benjamin Rebuffat; Vincenzo Della Marca; Pascal Masson; Jean-Luc Ogier; Marc Mantelli; Olivier Paulet; Laurent Lopez; Romain Laffont (ESSDERC, 2013)

Effect of AC stress on oxide TDDB and trapped charge in interface states. - Benjamin Rebuffat; Pascal Masson; Jean-Luc Ogier; Marc Mantelli; Romain Laffont (ISIC, 2014)

Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology. - Jordan Innocenti; Loic Welter; Franck Julien; Laurent Lopez; Jacques Sonzogni; Stephan Niel; Arnaud Régnier; Emmanuel Paire; Karen Labory; Eric Denis; Jean-Michel Portal; Pascal Masson (MWSCAS, 2014)

Layout optimizations to decrease internal power and area in digital CMOS standard cells. - Jordan Innocenti; Franck Julien; Jean-Michel Portal; Laurent Lopez; Q. Hubert; Pascal Masson; Jacques Sonzogni; Stephan Niel; Arnaud Régnier (MIPRO, 2015)

Dynamic current reduction of CMOS digital circuits through design and process optimization. - Jordan Innocenti; Loïc Welter; Nicolas Borrel; Franck Julien; Jean-Michel Portal; Jacques Sonzogni; Laurent Lopez; Pascal Masson; Stephan Niel; Philippe Dreux; Julia Castellan (PATMOS, 2015)

Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip. - Thibault Kempf; Vincenzo Della Marca; L. Baron; F. Maugain; Francesco La Rosa; Stephan Niel; Arnaud Régnier; Jean-Michel Portal; Pascal Masson (IRPS, 2018)

A Schmitt trigger to benchmark the performance of a new zero-cost transistor. - Paul Devoge; Hassen Aziza; Philippe Lorenzini; Pascal Masson; Alexandre Malherbe; Franck Julien; Abderrezak Marzaki; Arnaud Régnier; Stephan Niel (ICECS 2022, 2022)

Notched gate MOSFET for capacitance reduction in RF SOI technology. - Lucas Antunes Tambara; Pascal Masson; Julien Amouroux; Stéphane Monfray; Julien Dura; Frederic Gianesello; Julien Babic; Romain Debroucke; Loic Welter; Siddhartha Dhar; Bernadette Gros; Clement Charbuillet; et al. (DTTIS, 2023)

40nm SONOS Embedded Select in Trench Memory. - Radouane Habhab; Vincenzo Della Marca; Pascal Masson; Nadia Miridi; Clement Pribat; Simon Jeannot; Thibault Kempf; Marc Mantelli; Philippe Lorenzini; Jean-Marc Voisin; Arnaud Régnier; Stephan Niel; et al. (ESSDERC, 2023)

MOSFET electron mobility enhancement using source/drain recess. - Lucas Antunes Tambara; Paul Devoge; Pascal Masson; Julien Amouroux; Julien Dura; C. Rivero; Franck Julien (DTTIS, 2024)