A Parallel VLSI Architecture for 1-Gb/s, 2048-b, Rate-1/2 Turbo Gallager Code Decoder. - Pasquale Ciao; Giulio Colavolpe; Luca Fanucci (DSD, 2004)

Layered Decoding of Non-Layered LDPC Codes. - Massimo Rovini; Francesco Rossi; Pasquale Ciao; Nicola E. L'Insalata; Luca Fanucci (DSD, 2006)

VLSI Design of a Fully-Parallel High-Throughput Decoder for Turbo Gallager Codes. - Luca Fanucci; Pasquale Ciao; Giulio Colavolpe (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)