A comprehensive submicrometer MOST delay model and its application to CMOS buffers. - Pasquale Cocchini; Gianluca Piccinini; Maurizio Zamboni (IEEE J. Solid State Circuits, 1997)

Fanout optimization under a submicron transistor-level delay model. - Pasquale Cocchini; Massoud Pedram; Gianluca Piccinini; Maurizio Zamboni (ICCAD, 1998)

Fanout optimization using bipolar LT-trees. - Pasquale Cocchini; Massoud Pedram (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Concurrent flip-flop and repeater insertion for high performance integrated circuits. - Pasquale Cocchini (ICCAD, 2002)

The scaling challenge: can correct-by-construction design help? - Prashant Saxena; Noel Menezes; Pasquale Cocchini; Desmond Kirkpatrick (ISPD, 2003)

A methodology for optimal repeater insertion in pipelined interconnects. - Pasquale Cocchini (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Repeater scaling and its impact on CAD. - Prashant Saxena; Noel Menezes; Pasquale Cocchini; Desmond Kirkpatrick (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

RHNAS: Realizable Hardware and Neural Architecture Search. - Yash Akhauri; Adithya Niranjan; J. Pablo Muñoz; Suvadeep Banerjee; Abhijit Davare; Pasquale Cocchini; Anton A. Sorokin; Ravi Iyer 001; Nilesh Jain (CoRR, 2021)

A Highly Configurable Hardware/Software Stack for DNN Inference Acceleration. - Suvadeep Banerjee; Steve Burns 002; Pasquale Cocchini; Abhijit Davare; Shweta Jain 005; Desmond Kirkpatrick; Anton Sorokin; Jin Yang 006; Zhenkun Yang (CoRR, 2021)

Accelerator design with decoupled hardware customizations: benefits and challenges: invited. - Debjit Pal; Yi-Hsiang Lai; Shaojie Xiang; Niansong Zhang; Hongzheng Chen; Jeremy Casas; Pasquale Cocchini; Zhenkun Yang; Jin Yang 006; Louis-Noël Pouchet; Zhiru Zhang (DAC, 2022)

An Equivalence Checking Framework for Agile Hardware Design. - Yanzhao Wang; Fei Xie 004; Zhenkun Yang; Pasquale Cocchini; Jin Yang 006 (ASP-DAC, 2023)

An Automated Verification Framework for HalideIR-Based Compiler Transformations. - Yanzhao Wang; Fei Xie 004; Zhenkun Yang; Jeremy Casas; Pasquale Cocchini; Jin Yang 006 (DATE, 2023)

Towards A Correct-by-Construction FHE Model. - Zhenkun Yang; Wen Wang; Jeremy Casas; Pasquale Cocchini; Jin Yang 006 (IACR Cryptol. ePrint Arch., 2023)

A Systematic Translation Validation Framework for MLIR-Based Compilers. - Yanzhao Wang; Fei Xie 004; Zhenkun Yang; Pasquale Cocchini; Jin Yang 006 (Int. J. Softw. Eng. Knowl. Eng., 2024)