High performance VLSI modules for division and square root. - Gregorio Cappuccino; Pasquale Corsonello; Giuseppe Cocorullo (Microprocess. Microsystems, 1998)

A 56-bit self-timed adder for high speed asynchronous datapath. - Pasquale Corsonello; Stefania Perri; Giuseppe Cocorullo (ICECS, 1999)

Designing High-Speed Asynchronous Pipelines. - Stefania Perri; Pasquale Corsonello; Giuseppe Cocorullo (EUROMICRO, 2000)

VLSI Implementation of a Low-Power High-Speed Self-Timed Adder. - Pasquale Corsonello; Stefania Perri; Giuseppe Cocorullo (PATMOS, 2000)

Area-time-power tradeoff in cellular arrays VLSI implementations. - Pasquale Corsonello; Stefania Perri; G. Cororullo (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Dynamic power of CMOS gates driving lossy transmission lines. - Gregorio Cappuccino; Pasquale Corsonello; Giuseppe Cocorullo; Stefania Perri; Giovanni Staino (ICECS, 2001)

VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits. - Stefania Perri; Pasquale Corsonello; Giuseppe Cocorullo; Gregorio Cappuccino; Giovanni Staino (ICECS, 2001)

Speed-efficient wide adders for VIRTEX FPGAs. - Stefania Perri; Maria Antonia Iachino; Pasquale Corsonello (ICECS, 2002)

Efficient Implementation of Cellular Algorithms on Reconfigurable Hardware. - Pasquale Corsonello; Giandomenico Spezzano; Giovanni Staino; Domenico Talia (PDP, 2002)

VLSI circuits for low-power high-speed asynchronous addition. - Stefania Perri; Pasquale Corsonello; Giuseppe Cocorullo (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems. - Pasquale Corsonello; Stefania Perri; Maria Antonia Iachino; Giuseppe Cocorullo (FPL, 2003)

A low-power sub-nanosecond standard-cells based adder. - Stefania Perri; Pasquale Corsonello; Giovanni Staino (ICECS, 2003)

A high-speed energy-efficient 64-bit reconfigurable binary adder. - Stefania Perri; Pasquale Corsonello; Giuseppe Cocorullo (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Area- and Power-Reduced Standard-Cell Spanning Tree Adders. - Pasquale Corsonello; Stefania Perri; Vitit Kantabutra (ESA/VLSI, 2004)

FPGA implementation of Bayesian neural networks for a stand-alone predictor of pollutants concentration in the air. - Salvatore Marra; Francesco Carlo Morabito; Pasquale Corsonello; Mario Versaci (IJCNN, 2004)

Variable precision arithmetic circuits for FPGA-based multimedia processors. - Stefania Perri; Pasquale Corsonello; Maria Antonia Iachino; Marco Lanuzza; Giuseppe Cocorullo (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor. - Marco Lanuzza; Stefania Perri; Martin Margala; Pasquale Corsonello (FPL, 2005)

Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications. - Marco Lanuzza; Martin Margala; Pasquale Corsonello (ISLPED, 2005)

Fast Low-Power 64-Bit Modular Hybrid Adder. - Stefania Perri; Pasquale Corsonello; Giuseppe Cocorullo (PATMOS, 2005)

Efficient Reconfigurable Manchester Adders for Low-power Media Processing. - Pasquale Corsonello; Stefania Perri (J. Circuits Syst. Comput., 2005)

Microprocessor-based FPGA implementation of SPIHT image compression subsystems. - Pasquale Corsonello; Stefania Perri; Paolo Zicari; Giuseppe Cocorullo (Microprocess. Microsystems, 2005)

A high-performance fully reconfigurable FPGA-based 2D convolution processor. - Stefania Perri; Marco Lanuzza; Pasquale Corsonello; Giuseppe Cocorullo (Microprocess. Microsystems, 2005)

Efficient Addition Circuits for Modular Design of Processors-in-Memory. - Pasquale Corsonello; Stefania Perri; Martin Margala (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

SAD-Based Stereo Matching Circuit for FPGAs. - Stefania Perri; Daniela Colonna; Paolo Zicari; Pasquale Corsonello (ICECS, 2006)

An Efficient Bit-Detection and Timing Recovery Circuit for FPGAs. - Paolo Zicari; Pasquale Corsonello; Stefania Perri (ICECS, 2006)

An integrated countermeasure against differential power analysis for secure smart-cards. - Pasquale Corsonello; Stefania Perri; Martin Margala (ISCAS, 2006)

Leakage energy reduction techniques in deep submicron cache memories: a comparative study. - Fabio Frustaci; Pasquale Corsonello; Stefania Perri; Giuseppe Cocorullo (ISCAS, 2006)

Simd Multipliers for Accelerating Embedded Processors in FPGAS. - Stefania Perri; Maria Antonia Iachino; Pasquale Corsonello (J. Circuits Syst. Comput., 2006)

Low bit rate image compression core for onboard space applications. - Pasquale Corsonello; Stefania Perri; Giovanni Staino; Marco Lanuzza; Giuseppe Cocorullo (IEEE Trans. Circuits Syst. Video Technol., 2006)

Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories. - Fabio Frustaci; Pasquale Corsonello; Stefania Perri; Giuseppe Cocorullo (IEEE Trans. Very Large Scale Integr. Syst., 2006)

A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications. - Marco Lanuzza; Stefania Perri; Pasquale Corsonello; Martin Margala (AHS, 2007)

Design and Implementation of a 90nm Low bit-rate Image Compression Core. - Pasquale Corsonello; Stefania Perri; Giovanni Staino; Marco Lanuzza; Giuseppe Cocorullo (DSD, 2007)

An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector. - Emanuele Sciagura; Paolo Zicari; Stefania Perri; Pasquale Corsonello (DSD, 2007)

MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing. - Marco Lanuzza; Stefania Perri; Pasquale Corsonello (SAMOS, 2007)

VLSI implementations of efficient isotropic flexible 2D convolvers. - Stefania Perri; Pasquale Corsonello (IET Circuits Devices Syst., 2007)

A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation. - Fabio Frustaci; Pasquale Corsonello; Stefania Perri; Giuseppe Cocorullo (PATMOS, 2008)

Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. - Marco Lanuzza; Stefania Perri; Pasquale Corsonello; Martin Margala (PATMOS, 2008)

Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices. - Sohan Purohit; Sai Rahul Chalamalasetti; Martin Margala; Pasquale Corsonello (ReConFig, 2008)

Power/throughput/area efficient PIM-based reconfigurable array for parallel processing. - Sohan Purohit; Sai Rahul Chalamalasetti; Martin Margala; Pasquale Corsonello (SoCC, 2008)

High-performance noise-tolerant circuit techniques for CMOS dynamic logic. - Fabio Frustaci; Pasquale Corsonello; Stefania Perri; Giuseppe Cocorullo (IET Circuits Devices Syst., 2008)

A matrix product accelerator for field programmable systems on chip. - Paolo Zicari; Pasquale Corsonello; Stefania Perri; Giuseppe Cocorullo (Microprocess. Microsystems, 2008)

A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals. - Paolo Zicari; Emanuele Sciagura; Stefania Perri; Pasquale Corsonello (Microprocess. Microsystems, 2008)

Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator. - Stefania Perri; Pasquale Corsonello (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications. - Marco Lanuzza; Paolo Zicari; Fabio Frustaci; Stefania Perri; Pasquale Corsonello (ARC, 2009)

New performance/power/area efficient, reliable full adder design. - Sohan Purohit; Martin Margala; Marco Lanuzza; Pasquale Corsonello (ACM Great Lakes Symposium on VLSI, 2009)

Quad-Port Memory Blocks in Radiation-Tolerant FPGAs: An Application for Image Processing Systems. - Aakash Jain; Giovanni Staino; Pasquale Corsonello (ICETET, 2009)

Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. - Sohan Purohit; Marco Lanuzza; Stefania Perri; Pasquale Corsonello; Martin Margala (VLSI Design, 2009)

Low-power split-path data-driven dynamic logic. - Fabio Frustaci; Marco Lanuzza; Paolo Zicari; Stefania Perri; Pasquale Corsonello (IET Circuits Devices Syst., 2009)

Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems. - Sohan Purohit; Marco Lanuzza; Stefania Perri; Pasquale Corsonello; Martin Margala (J. Low Power Electron., 2009)

Designing High-Speed Adders in Power-Constrained Environments. - Fabio Frustaci; Marco Lanuzza; Paolo Zicari; Stefania Perri; Pasquale Corsonello (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Impact of Random Process Variations on Different 65nm SRAM Cell Topologies. - Sumit Kansal; Marco Lanuzza; Pasquale Corsonello (ICETET, 2010)

A Low-Leakage Single-Ended 6T SRAM Cell. - Sohit Solanki; Fabio Frustaci; Pasquale Corsonello (ICETET, 2010)

A new low-power high-speed single-clock-cycle binary comparator. - Fabio Frustaci; Stefania Perri; Marco Lanuzza; Pasquale Corsonello (ISCAS, 2010)

Impact of Process Variations on Flip-Flops Energy and Timing Characteristics. - Marco Lanuzza; Raffaele De Rose; Fabio Frustaci; Stefania Perri; Pasquale Corsonello (ISVLSI, 2010)

Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis. - Marco Lanuzza; Raffaele De Rose; Fabio Frustaci; Stefania Perri; Pasquale Corsonello (PATMOS, 2010)

Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications. - Marco Lanuzza; Paolo Zicari; Fabio Frustaci; Stefania Perri; Pasquale Corsonello (ACM Trans. Reconfigurable Technol. Syst., 2010)

Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffers. - Fabio Frustaci; Pasquale Corsonello; Massimo Alioto (ECCTD, 2011)

Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technology. - Fabio Frustaci; Pasquale Corsonello; Massimo Alioto (ISCAS, 2011)

Efficient memory architecture for image processing. - Stefania Perri; Pasquale Corsonello (Int. J. Circuit Theory Appl., 2011)

Fast-squarer circuits using 3-bit-scan without overlapping bits. - Stefania Perri; Pasquale Corsonello (Int. J. Circuit Theory Appl., 2011)

A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference. - Luca Magnelli; Felice Crupi; Pasquale Corsonello; Calogero Pace; Giuseppe Iannaccone (IEEE J. Solid State Circuits, 2011)

Tapered-Vth Approach for Energy-Efficient CMOS Buffers. - Fabio Frustaci; Massimo Alioto; Pasquale Corsonello (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Energy-efficient single-clock-cycle binary comparator. - Fabio Frustaci; Stefania Perri; Marco Lanuzza; Pasquale Corsonello (Int. J. Circuit Theory Appl., 2012)

Low-cost FPGA stereo vision system for real time disparity maps calculation. - Paolo Zicari; Stefania Perri; Pasquale Corsonello; Giuseppe Cocorullo (Microprocess. Microsystems, 2012)

Comparative analysis of yield optimized pulsed flip-flops. - Marco Lanuzza; Raffaele De Rose; Fabio Frustaci; Stefania Perri; Pasquale Corsonello (Microelectron. Reliab., 2012)

Analytical Delay Model Considering Variability Effects in Subthreshold Domain. - Fabio Frustaci; Pasquale Corsonello; Stefania Perri (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Low-Power Level Shifter for Multi-Supply Voltage Designs. - Marco Lanuzza; Pasquale Corsonello; Stefania Perri (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Adaptive Census Transform: A novel hardware-oriented stereovision algorithm. - Stefania Perri; Pasquale Corsonello; Giuseppe Cocorullo (Comput. Vis. Image Underst., 2013)

A novel background subtraction method based on color invariants and grayscale levels. - Lorena Guachi; Giuseppe Cocorullo; Pasquale Corsonello; Fabio Frustaci; Stefania Perri (ICCST, 2014)

Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates. - Pasquale Corsonello; Marco Lanuzza; Stefania Perri (Int. J. Circuit Theory Appl., 2014)

Analyzing noise robustness of wide fan-in dynamic logic gates under process variations. - Fabio Frustaci; Marco Lanuzza; Stefania Perri; Pasquale Corsonello (Int. J. Circuit Theory Appl., 2014)

Design of high-speed low-power parallel-prefix adder trees in nanometer technologies. - Stefania Perri; Marco Lanuzza; Pasquale Corsonello (Int. J. Circuit Theory Appl., 2014)

Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain. - Pasquale Corsonello; Fabio Frustaci; Marco Lanuzza; Stefania Perri (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Area-Delay Efficient Binary Adders in QCA. - Stefania Perri; Pasquale Corsonello; Giuseppe Cocorullo (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Exploring well configurations for voltage level converter design in 28 nm UTBB FDSOI technology. - Pasquale Corsonello; Stefania Perri; Fabio Frustaci (ICCD, 2015)

Novel Varactor-Loaded Phasing Line for Reflectarray Unit Cell with Large Reconfigurability Frequency Range. - Sandra Costanzo; Francesca Venneri; Antonio Raffo; Giuseppe Di Massa; Pasquale Corsonello (WorldCIST (2), 2015)

A sub-1 V nanopower temperature-compensated sub-threshold CMOS voltage reference with 0.065%/V line sensitivity. - Luca Magnelli; Felice Crupi; Pasquale Corsonello; Giuseppe Iannaccone (Int. J. Circuit Theory Appl., 2015)

Power supply noise in accurate delay model for the sub-threshold domain. - Pasquale Corsonello; Fabio Frustaci; Stefania Perri (Integr., 2015)

Low-Leakage SRAM Wordline Drivers for the 28-nm UTBB FDSOI Technology. - Pasquale Corsonello; Fabio Frustaci; Stefania Perri (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs. - Marco Lanuzza; Pasquale Corsonello; Stefania Perri (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Design of efficient QCA multiplexers. - Giuseppe Cocorullo; Pasquale Corsonello; Fabio Frustaci; Stefania Perri (Int. J. Circuit Theory Appl., 2016)

An efficient hardware-oriented stereo matching algorithm. - Giuseppe Cocorullo; Pasquale Corsonello; Fabio Frustaci; Stefania Perri (Microprocess. Microsystems, 2016)

Design of Efficient BCD Adders in Quantum-Dot Cellular Automata. - Giuseppe Cocorullo; Pasquale Corsonello; Fabio Frustaci; Stefania Perri (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Editorial. - Krishnendu Chakrabarty; Massimo Alioto; Bevan M. Baas; Chirn Chye Boon; Meng-Fan Chang; Naehyuck Chang; Yao-Wen Chang; Chip-Hong Chang; Shih-Chieh Chang; Poki Chen; Masud H. Chowdhury; Pasquale Corsonello; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems. - Fanny Spagnolo; Stefania Perri; Fabio Frustaci; Pasquale Corsonello (ICECS, 2018)

Designing Fast Convolutional Engines for Deep Learning Applications. - Fanny Spagnolo; Stefania Perri; Fabio Frustaci; Pasquale Corsonello (ICECS, 2018)

Design of Real-Time FPGA-based Embedded System for Stereo Vision. - Stefania Perri; Fabio Frustaci; Fanny Spagnolo; Pasquale Corsonello (ISCAS, 2018)

Efficient Architecture for Integral Image Computation on Heterogeneous FPGAs. - Fanny Spagnolo; Pasquale Corsonello; Stefania Perri (PRIME, 2019)

Multimodal background subtraction for high-performance embedded systems. - Giuseppe Cocorullo; Pasquale Corsonello; Fabio Frustaci; Lorena-de-los-Angeles Guachi-Guachi; Stefania Perri (J. Real Time Image Process., 2019)

An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis. - Fanny Spagnolo; Stefania Perri; Pasquale Corsonello (Sensors, 2019)

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. - Massimo Alioto; Magdy S. Abadir; Tughrul Arslan; Chirn Chye Boon; Andreas Burg 001; Chip-Hong Chang; Meng-Fan Chang; Yao-Wen Chang; Poki Chen; Pasquale Corsonello; Paolo Crovetti; Shiro Dosho; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation. - Fabio Frustaci; Stefania Perri; Pasquale Corsonello; Massimo Alioto (IEEE Trans. Very Large Scale Integr. Syst., 2019)

An Efficient Convolution Engine based on the À-trous Spatial Pyramid Pooling. - Cristian Sestito; Fanny Spagnolo; Pasquale Corsonello; Stefania Perri (ASAP, 2020)

A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs. - Fanny Spagnolo; Fabio Frustaci; Stefania Perri; Pasquale Corsonello (ICECS, 2020)

Reconfigurable Convolution Architecture for Heterogeneous Systems-on-Chip. - Fanny Spagnolo; Stefania Perri; Fabio Frustaci; Pasquale Corsonello (MECO, 2020)

Parallel architecture of power-of-two multipliers for FPGAs. - Stefania Perri; Fanny Spagnolo; Fabio Frustaci; Pasquale Corsonello (IET Circuits Devices Syst., 2020)

Design of a real-time face detection architecture for heterogeneous systems-on-chips. - Fanny Spagnolo; Stefania Perri; Pasquale Corsonello (Integr., 2020)

Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip. - Stefania Perri; Cristian Sestito; Fanny Spagnolo; Pasquale Corsonello (J. Imaging, 2020)

Stereo vision architecture for heterogeneous systems-on-chip. - Stefania Perri; Fabio Frustaci; Fanny Spagnolo; Pasquale Corsonello (J. Real Time Image Process., 2020)

Approximate Multipliers With Dynamic Truncation for Energy Reduction via Graceful Quality Degradation. - Fabio Frustaci; Stefania Perri; Pasquale Corsonello; Massimo Alioto (IEEE Trans. Circuits Syst., 2020)

Accuracy Improved Low-Energy Multi-Bit Approximate Adders in QCA. - Stefania Perri; Fanny Spagnolo; Fabio Frustaci; Pasquale Corsonello (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

ERMES: Efficient Racetrack Memory Emulation System based on FPGA. - Fanny Spagnolo; Salim Ullah; Pasquale Corsonello; Akash Kumar 001 (FPL, 2022)

Heterogeneous FPGA-based System for Real-Time Drowsiness Detection. - Andrea Migali; Fanny Spagnolo; Pasquale Corsonello (PRIME, 2022)

Hardware-Oriented Multi-Exposure Fusion Approach for Real-Time Video Processing on FPGA. - Mario Andrea Sangiovanni; Fanny Spagnolo; Pasquale Corsonello (PRIME, 2022)

Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems. - Fanny Spagnolo; Stefania Perri; Pasquale Corsonello (IEEE Access, 2022)

Robust and High-Performance Machine Vision System for Automatic Quality Inspection in Assembly Processes. - Fabio Frustaci; Fanny Spagnolo; Stefania Perri; Giuseppe Cocorullo; Pasquale Corsonello (Sensors, 2022)

Multibit Full Comparator Logic in Quantum-Dot Cellular Automata. - Stefania Perri; Fanny Spagnolo; Fabio Frustaci; Pasquale Corsonello (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Aggressive Approximation of the SoftMax Function for Power-Efficient Hardware Implementations. - Fanny Spagnolo; Stefania Perri; Pasquale Corsonello (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Secure and Energy-Efficient ECG Signal Monitoring in the IoT Healthcare using Compressive Sensing. - Bharat Lal; Miguel Heredia Conde; Pasquale Corsonello; Raffaele Gravina (DASC/PiCom/CBDCom/CyberSciTech, 2023)

Abnormal ECG Detection in Wearable Devices Using Compressed Learning. - Bharat Lal; Qimeng Li; Pasquale Corsonello; Raffaele Gravina (ICNSC, 2023)

Design of Approximate Bilateral Filters for Image Denoising on FPGAs. - Fanny Spagnolo; Pasquale Corsonello; Fabio Frustaci; Stefania Perri (IEEE Access, 2023)

A High-Speed FPGA-Based True Random Number Generator Using Metastability With Clock Managers. - Fabio Frustaci; Fanny Spagnolo; Stefania Perri; Pasquale Corsonello (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Design of Leading Zero Counters on FPGAs. - Stefania Perri; Fanny Spagnolo; Fabio Frustaci; Pasquale Corsonello (IEEE Embed. Syst. Lett., 2023)

KIT: Kernel Isotropic Transformation of Bilateral Filters for Image Denoising on FPGA. - Fanny Spagnolo; Pasquale Corsonello; Fabio Frustaci; Stefania Perri (FPL, 2024)

Carry-chain based Ring Oscillator Design for Temperature Sensing on FPGAs. - Fanny Spagnolo; Pasquale Corsonello (SMACD, 2024)

Efficient implementation of signed multipliers on FPGAs. - Fanny Spagnolo; Pasquale Corsonello; Fabio Frustaci; Stefania Perri (Comput. Electr. Eng., 2024)

An explainable embedded neural system for on-board ship detection from optical satellite imagery. - Cosimo Ieracitano; Nadia Mammone; Fanny Spagnolo; Fabio Frustaci; Stefania Perri; Pasquale Corsonello; Francesco Carlo Morabito (Eng. Appl. Artif. Intell., 2024)

Approximate bilateral filters for real-time and low-energy imaging applications on FPGAs. - Fanny Spagnolo; Pasquale Corsonello; Fabio Frustaci; Stefania Perri (J. Supercomput., 2024)

Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization. - Fanny Spagnolo; Stefania Perri; Massimo Vatalaro; Fabio Frustaci; Felice Crupi; Pasquale Corsonello (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations. - Fabio Frustaci; Fanny Spagnolo; Pasquale Corsonello; Stefania Perri (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Multi-Partner Project: Architectures and Design Methodologies to Accelerate AI Workloads. The ICSC Flagship 2 Project. - Cristina Silvano; Fabrizio Ferrandi; Serena Curzel; Daniele Ielmini; Stefania Perri; Fanny Spagnolo; Pasquale Corsonello; Sebastiano Fabio Schifano; Cristian Zambelli; Angelo Garofalo; Francesco Conti 001; Luca Benini (DATE, 2025)

Approximate Swish Activation Function for Low-Energy Yet Low-Error VLSI Implementations. - Fanny Spagnolo; Stefania Perri; Pasquale Corsonello (ISVLSI, 2025)

Data-driven compressive sensing approach for ECG signals in IoT healthcare applications. - Bharat Lal; Pasquale Corsonello; Raffaele Gravina (Internet Things, 2025)

C4TERO: Configurable Cascaded Carry Chains for High Reliability TERO PUFs on FPGAs. - Fanny Spagnolo; Massimo Vatalaro; Stefania Perri; Felice Crupi; Pasquale Corsonello (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Novel Compressive Sensing Method for Secure and Energy Efficient ECG Signal Transmission Applications. - Fanny Spagnolo; Bharat Lal; Pasquale Corsonello; Raffaele Gravina (IEEE J. Biomed. Health Informatics, 2025)

HIMAM: Hardware Implementation of Multiply-and-Max/Min Layers for Energy-Efficient DNN Inference. - Fanny Spagnolo; Pasquale Corsonello; Stefania Perri (IEEE Trans. Circuits Syst. II Express Briefs, 2025)