Design procedure for DVB-T receivers large tuning range LP filter. - Pasquale Delizia; Marcello De Matteis; Stefano D'Amico; Andrea Baschirotto; Carlos Azeredo Leme; Ricardo Reis 001 (ISCAS, 2008)

A 10-b 100-MS/s pipelined ADC with an optimized bit-stage resolution in 65nm CMOS technology. - Pasquale Delizia; Gianni Saccomanno; Stefano D'Amico; Andrea Baschirotto (ISCAS, 2010)

9.8 A 9.3nV/rtHz 20b 40MS/s 94.2dB DR Signal-Chain Friendly Precision SAR Converter. - Rares Bodnar; Henry Kennedy 001; Christopher P. Hurrell; Asif Ahmad; Mark Vickery; Luke Smithers; William Buckley; Monsoon Dutt; Pasquale Delizia; Derek Hummerston; Pawel Czapor (ISSCC, 2024)