Patrícia Ücker

Orcid: 0000-0001-5121-7101

According to our database1, Patrícia Ücker authored at least 17 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
VLSI Architectures of Approximate Arithmetic Units Applied to Parallel Sensors Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

2023
AxPPA: Approximate Parallel Prefix Adders.
IEEE Trans. Very Large Scale Integr. Syst., 2023

An Energy-Efficient StEFCal VLSI Design with Approximate Squarer and Divider Units.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023

An Optimized VLSI Exponential Unit Design Exploring Efficient Arithmetic Operation Strategies.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2022
Energy-Quality Scalable Design Space Exploration of Approximate FFT Hardware Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Improved Approximate Multipliers for Single-Precision Floating-Point Hardware Design.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

An Efficient Exponential Unit Designed in VLSI CMOS with Custom Operators.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021
Architectural Exploration for Energy-Efficient Fixed-Point Kalman Filter VLSI Design.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Fixed-Point NLMS and IPNLMS VLSI Architectures for Accurate FECG and FHR Processing.
IEEE Trans. Biomed. Circuits Syst., 2021

Exploring NLMS-Based Adaptive Filter Hardware Architectures for Eliminating Power Line Interference in EEG Signals.
Circuits Syst. Signal Process., 2021

Boosting the Efficiency of the Harmonics Elimination VLSI Architecture by Arithmetic Approximations.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020
Optimizing the Montgomery Modular Multiplier for a Power- and Area-Efficient Hardware Architecture.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Optimizing Iterative-based Dividers for an Efficient Natural Logarithm Operator Design.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

An Efficient N-bit 8-2 Adder Compressor with a Constant Internal Carry Propagation Delay.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

Exploring NLMS and IPNLMS Adaptive Filtering VLSI Hardware Architectures for Robust EEG Signal Artifacts Elimination.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

An Efficient NLMS-based VLSI Architecture for Robust FECG Extraction and FHR Processing.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019
Exploring Architectural Solutions for an Energy-Efficient Kalman Filter Gain Realization.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019


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