Low-power area-efficient high-speed I/O circuit techniques. - Ming-Ju Edward Lee; William J. Dally; Patrick Chiang 001 (IEEE J. Solid State Circuits, 2000)

Monolithic chaotic communications system. - Patrick Chiang 001; William J. Dally; Ming-Ju Edward Lee (ISCAS (3), 2001)

A 20-Gb/s 0.13-μm CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer. - Patrick Chiang 001; William J. Dally; Ming-Ju Edward Lee; Ramesh Senthinathan; Yangjin Oh; Mark A. Horowitz (IEEE J. Solid State Circuits, 2005)

Process Variation Compensation of a 2.4GHz LNA in 0.18um CMOS Using Digitally Switchable Capacitance. - Yike Cui; Baoyong Chi; Minjie Liu; Yulei Zhang; Yongming Li 004; Zhihua Wang 001; Patrick Chiang 001 (ISCAS, 2007)

NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication. - Tushar Krishna; Amit Kumar 002; Patrick Chiang 001; Mattan Erez; Li-Shiuan Peh (Hot Interconnects, 2008)

A 10Gb/s Wire-line Transceiver with Half Rate Period Calibration CDR. - Zhuo Gao; Hang Yu; Patrick Chiang 001; Yi Yang; Feng Zhang 014 (ISCAS, 2009)

Comparison of On-die Global Clock Distribution Methods for Parallel Serial Links. - Kangmin Hu; Tao Jiang 005; Patrick Chiang 001 (ISCAS, 2009)

Sense Amplifier Power and Delay Characterization for Operation under Low-Vdd and Low-voltage Clock Swing. - Tao Jiang 005; Patrick Yin Chiang (ISCAS, 2009)

Measuring and Compensating for Process Mismatch-induced, Reference Spurs in Phase-locked Loops using a Sub-sampled DSP. - Zhuo Gao; D. Kesharwani; Patrick Chiang 001; Weiwu Hu (ISCAS, 2009)

Express Virtual Channels with Capacitively Driven Global Links. - Tushar Krishna; Amit Kumar 002; Li-Shiuan Peh; Jacob Postman; Patrick Chiang 001; Mattan Erez (IEEE Micro, 2009)

A 0.18-muhboxm CMOS GFSK Analog Front End Using a Bessel-Based Quadrature Discriminator With On-Chip Automatic Tuning. - Baoyong Chi; Jinke Yao; Patrick Chiang 001; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A Fast-Settling Wideband-IF ASK Baseband Circuit for a Wireless Endoscope Capsule. - Baoyong Chi; Jinke Yao; Patrick Chiang 001; Zhihua Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOS. - Tao Jiang 005; Wing Liu; Freeman Y. Zhong; Charlie Zhong; Patrick Yin Chiang (CICC, 2010)

SWIFT: A SWing-reduced interconnect for a Token-based Network-on-Chip in 90nm CMOS. - Tushar Krishna; Jacob Postman; Christopher Edmonds; Li-Shiuan Peh; Patrick Chiang 001 (ICCD, 2010)

Synctium: a Near-Threshold Stream Processor for Energy-Constrained Parallel Applications. - Evgeni Krimer; Robert Pawlowski; Mattan Erez; Patrick Chiang 001 (IEEE Comput. Archit. Lett., 2010)

Short-Range, Wireless Interconnect within a Computing Chassis: Design Challenges. - Patrick Yin Chiang; Sirikarn Woracheewan; Changhui Hu 003; Lei Guo; Rahul Khanna; Jay J. Nejedlo; Huaping Liu 002 (IEEE Des. Test Comput., 2010)

A 0.6 mW/Gb/s, 6.4-7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS. - Kangmin Hu; Tao Jiang 005; Jingguang Wang; Frank O'Mahony; Patrick Yin Chiang (IEEE J. Solid State Circuits, 2010)

Chaotic Pulse-Position Baseband Modulation for an Ultra-Wideband Transceiver in CMOS. - Patrick Yin Chiang; Changhui Hu 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

All-digital 3-50 GHz ultra-wideband pulse generator for short-range wireless interconnect in 40nm CMOS. - Changhui Hu 003; Patrick Yin Chiang (CICC, 2011)

Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOS. - Kangmin Hu; Tao Jiang 005; Samuel Palermo; Patrick Yin Chiang (CICC, 2011)

Energy-efficient transceiver circuits for short-range on-chip interconnects. - Jacob Postman; Patrick Chiang 001 (CICC, 2011)

An energy-efficient 64-QAM MIMO detector for emerging wireless standards. - Nariman Moezzi Madani; Thorlindur Thorolfsson; Joseph Crop; Patrick Chiang 001; W. Rhett Davis (DATE, 2011)

OLAM: A wearable, non-contact sensor for continuous heart-rate and activity monitoring. - Ryan K. Albright; Benjamin J. Goska; Tory M. Hagen; Yu Mike Chi; Gert Cauwenberghs; Patrick Yin Chiang (EMBC, 2011)

Indoor localization using pedestrian dead reckoning updated with RFID-based fiducials. - Samuel House; Sean Connell; Ian Milligan; Daniel Austin; Tamara L. Hayes; Patrick Chiang 001 (EMBC, 2011)

Design automation methodology for improving the variability of synthesized digital circuits operating in the sub/near-threshold regime. - Joseph Crop; Robert Pawlowski; Nariman Moezzi Madani; Jarrod Jackson; Patrick Chiang 001 (IGCC, 2011)

Network coding in multicore processors. - Thuan Duong-Ba; Thinh P. Nguyen; Patrick Chiang 001 (IPCCC, 2011)

Experimental Characterization of a UWB Channel for Body Area Networks. - Lingli Xia; Stephen Redfield; Patrick Chiang 001 (EURASIP J. Wirel. Commun. Netw., 2011)

100-phase, dual-loop delay-locked loop for impulse radio ultra-wideband coherent receiver synchronisation. - Lingli Xia; Hu Chen; Yumei Huang; Zhiliang Hong; Patrick Yin Chiang (IET Circuits Devices Syst., 2011)

Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links. - Ahmed Ragab; Yang Liu 178; Kangmin Hu; Patrick Chiang 001; Samuel Palermo (J. Electr. Comput. Eng., 2011)

A 90 nm-CMOS, 500 Mbps, 3-5 GHz Fully-Integrated IR-UWB Transceiver With Multipath Equalization Using Pulse Injection-Locking for Receiver Phase Synchronization. - Changhui Hu 003; Rahul Khanna; Jay J. Nejedlo; Kangmin Hu; Huaping Liu 002; Patrick Yin Chiang (IEEE J. Solid State Circuits, 2011)

Sinusoidal Clock Sampling for Multigigahertz ADCs. - Rui Bai 001; Jingguang Wang; Lingli Xia; Feng Zhang 014; Zongren Yang; Weiwu Hu; Patrick Chiang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A near-threshold, multi-node, wireless body area sensor network powered by RF energy harvesting. - Jiao Cheng; Lingli Xia; Chao Ma 020; Yong Lian 001; Xiaoyuan Xu; C. Patrick Yue; Zhiliang Hong; Patrick Yin Chiang (CICC, 2012)

Regaining throughput using completion detection for error-resilient, near-threshold logic. - Joseph Crop; Robert Pawlowski; Patrick Chiang 001 (DAC, 2012)

125Mbps ultra-wideband system evaluation for cortical implant devices. - Yi Luo; Chris Winstead; Patrick Chiang 001 (EMBC, 2012)

Location and activity tracking with the cloud. - Taj Morton; Alex Weeks; Samuel House; Patrick Chiang 001; Chris Scaffidi (EMBC, 2012)

Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures. - Evgeni Krimer; Patrick Chiang 001; Mattan Erez (ISCA, 2012)

A 12-bit 7 µW/channel 1 kHz/channel incremental ADC for biosensor interface circuits. - Chia-Hung Chen; Joseph Crop; Jeongseok Chae; Patrick Chiang 001; Gabor C. Temes (ISCAS, 2012)

A low-leakage dynamic register file with unclocked wordline and sub-segmentation for improved bitline scalability. - Eric Donkoh; Patrick Chiang 001 (ISLPED, 2012)

Register file write data gating techniques and break-even analysis model. - Eric Donkoh; Teck Siong Ong; Yan Nee Too; Patrick Chiang 001 (ISLPED, 2012)

A 530mV 10-lane SIMD processor with variation resiliency in 45nm SOI. - Robert Pawlowski; Evgeni Krimer; Joseph Crop; Jacob Postman; Nariman Moezzi Madani; Mattan Erez; Patrick Chiang 001 (ISSCC, 2012)

Innovative approach to server performance and power monitoring in data centers using wireless sensors (invited paper). - Rahul Khanna; Debabani Choudhury; Patrick Yin Chiang; Huaping Liu 002; Lingli Xia (RWS, 2012)

A low-power, capacitively-divided, ring oscillator with digitally adjustable voltage swing. - Tao Jiang 005; Kangmin Hu; Patrick Yin Chiang (VLSI-DAT, 2012)

0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking. - Kangmin Hu; Rui Bai 001; Tao Jiang 005; Chao Ma 020; Ahmed Ragab; Samuel Palermo; Patrick Yin Chiang (IEEE J. Solid State Circuits, 2012)

A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS. - Tao Jiang 005; Wing Liu; Freeman Y. Zhong; Charlie Zhong; Kangmin Hu; Patrick Yin Chiang (IEEE J. Solid State Circuits, 2012)

A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration. - Nan Qi; Yang Xu 005; Baoyong Chi; Yang Xu 039; Xiaobao Yu; Xing Zhang; Ni Xu; Patrick Chiang 001; Woogeun Rhee; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Sub-2-ps, Static Phase Error Calibration Technique Incorporating Measurement Uncertainty Cancellation for Multi-Gigahertz Time-Interleaved T/H Circuits. - Lingli Xia; Jingguang Wang; Will Beattie; Jacob Postman; Patrick Yin Chiang (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Power-Scalable, Complex Bandpass/Low-Pass Filter With I/Q Imbalance Calibration for a Multimode GNSS Receiver. - Yang Xu 005; Baoyong Chi; Xiaobao Yu; Nan Qi; Patrick Chiang 001; Zhihua Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A Comparative Study of 20-Gb/s NRZ and Duobinary Signaling Using Statistical Analysis. - Kangmin Hu; Larry Wu; Patrick Yin Chiang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Area-Efficient Antenna-Scalable MIMO Detector for K-best Sphere Decoding. - Nariman Moezzi Madani; Thorlindur Thorolfsson; Patrick Chiang 001; William Rhett Davis (J. Signal Process. Syst., 2012)

A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS. - Shuai Chen; Hao Li 047; Liqiong Yang; Zongren Yang; Weiwu Hu; Patrick Yin Chiang (CICC, 2013)

High-sensitivity photodetection sensor front-end, detecting organophosphourous compounds for food safety. - Lei Wan; Yajie Qin; Patrick Chiang 001; Guoping Chen; Ran Liu 001; Zhiliang Hong (CICC, 2013)

A ring-resonator-based silicon photonics transceiver with bias-based wavelength stabilization and adaptive-power-sensitivity receiver. - Cheng Li; Rui Bai 001; Ayman Shafik; Ehsan Zhian Tabasy; Geng Tang; Chao Ma 020; Chin-Hui Chen; Zhen Peng; Marco Fiorentino; Patrick Chiang 001; Samuel Palermo (ISSCC, 2013)

Comparison of hardware based and software based stress testing of memory IO interface. - Bruce Querbach; Sudeep Puligundla; Daniel Becerra; Zale T. Schoenborn; Patrick Chiang 001 (MWSCAS, 2013)

A 0.47-0.66 pJ/bit, 4.8-8 Gb/s I/O Transceiver in 65 nm CMOS. - Young-Hoon Song; Rui Bai 001; Kangmin Hu; Noah Hae-Woong Yang; Patrick Yin Chiang; Samuel Palermo (IEEE J. Solid State Circuits, 2013)

A Near-Threshold, 0.16 nJ/b OOK-Transmitter With 0.18 nJ/b Noise-Cancelling Super-Regenerative Receiver for the Medical Implant Communications Service. - Chao Ma 020; Changhui Hu 003; Jiao Cheng; Lingli Xia; Patrick Yin Chiang (IEEE Trans. Biomed. Circuits Syst., 2013)

SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects. - Jacob Postman; Tushar Krishna; Christopher Edmonds; Li-Shiuan Peh; Patrick Chiang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A 11μW 250 Hz BW two-step incremental ADC with 100 dB DR and 91 dB SNDR for integrated sensor interfaces. - Chia-Hung Chen; Yi Zhang 023; Tao He 001; Patrick Yin Chiang; Gabor C. Temes (CICC, 2014)

Energy-efficient bio-sensing systems. - Pedram Mohseni; Patrick Chiang 001 (CICC, 2014)

Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS. - Robert Pawlowski; Joseph Crop; Minki Cho; James W. Tschanz; Vivek De; Thomas Fairbanks; Heather Quinn; Shekhar Borkar; Patrick Yin Chiang (CICC, 2014)

A piezoelectric energy-harvesting shoe system for podiatric sensing. - Rich Meier; Nicholas Kelly; Omri Almog; Patrick Chiang 001 (EMBC, 2014)

A 41-mW 30-Gb/s CMOS optical receiver with digitally-tunable cascaded equalization. - Quan Pan 002; Yipeng Wang 003; Zhengxiong Hou; Li Sun; Liang Wu; Wing-Hung Ki; Patrick Chiang 001; C. Patrick Yue (ESSCIRC, 2014)

2.5 A 0.25pJ/b 0.7V 16Gb/s 3-tap decision-feedback equalizer in 65nm CMOS. - Rui Bai 001; Samuel Palermo; Patrick Yin Chiang (ISSCC, 2014)

9.6 A 1.3mW 0.6V WBAN-compatible sub-sampling PSK receiver in 65nm CMOS. - Jiao Cheng; Nan Qi; Patrick Yin Chiang; Arun Natarajan 001 (ISSCC, 2014)

26.5 An 8-to-16Gb/s 0.65-to-1.05pJ/b 2-tap impedance-modulated voltage-mode transmitter with fast power-state transitioning in 65nm CMOS. - Young-Hoon Song; Hae-Woong Yang; Hao Li 047; Patrick Yin Chiang; Samuel Palermo (ISSCC, 2014)

A reusable BIST with software assisted repair technology for improved memory and IO debug, validation and test time. - Bruce Querbach; Rahul Khanna; David Blankenbeckler; Yulan Zhang; Ronald T. Anderson; David G. Ellis; Zale T. Schoenborn; Sabyasachi Deyati; Patrick Chiang 001 (ITC, 2014)

A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS. - Hao Li 047; Shuai Chen; Liqiong Yang; Rui Bai 001; Weiwu Hu; Freeman Y. Zhong; Samuel Palermo; Patrick Yin Chiang (VLSIC, 2014)

A Low-Power, Low-Voltage WBAN-Compatible Sub-Sampling PSK Receiver in 65 nm CMOS. - Jiao Cheng; Nan Qi; Patrick Yin Chiang; Arun Natarajan 001 (IEEE J. Solid State Circuits, 2014)

Silicon Photonic Transceiver Circuits With Microring Resonator Bias-Based Wavelength Stabilization in 65 nm CMOS. - Cheng Li; Rui Bai 001; Ayman Shafik; Ehsan Zhian Tabasy; Binhao Wang; Geng Tang; Chao Ma 020; Chin-Hui Chen; Zhen Peng; Marco Fiorentino; Raymond G. Beausoleil; Patrick Chiang 001; et al. (IEEE J. Solid State Circuits, 2014)

An 8-16 Gb/s, 0.65-1.05 pJ/b, Voltage-Mode Transmitter With Analog Impedance Modulation Equalization and Sub-3 ns Power-State Transitioning. - Young-Hoon Song; Noah Hae-Woong Yang; Hao Li 047; Patrick Yin Chiang; Samuel Palermo (IEEE J. Solid State Circuits, 2014)

0.56 V, -20 dBm RF-Powered, Multi-Node Wireless Body Area Network System-on-a-Chip With Harvesting-Efficiency Tracking Loop. - Lingli Xia; Jiao Cheng; Neil E. Glover; Patrick Chiang 001 (IEEE J. Solid State Circuits, 2014)

A 20 μW dual-channel analog front-end in 65nm CMOS for portable ECG monitoring system. - Shuo Li; Nan Qi; Vahid Behravan; Zhiliang Hong; Patrick Yin Chiang (ASICON, 2015)

Rate-adaptive compressed-sensing and sparsity variance of biomedical signals. - Vahid Behravan; Neil E. Glover; Rutger Farry; Patrick Yin Chiang; Mohammed Shoaib (BSN, 2015)

A compressed-sensing sensor-on-chip incorporating statistics collection to improve reconstruction performance. - Vahid Behravan; Shuo Li; Neil E. Glover; Chia-Hung Chen; Mohammed Shoaib; Gabor C. Temes; Patrick Yin Chiang (CICC, 2015)

22.6 A 25Gb/s 4.4V-swing AC-coupled Si-photonic microring transmitter with 2-tap asymmetric FFE and dynamic thermal tuning in 65nm CMOS. - Hao Li 047; Zhe Xuan; Alex Titriku; Cheng Li; Kunzhi Yu; Binhao Wang; Ayman Shafik; Nan Qi; Yang Liu 178; Ran Ding; Tom Baehr Jones; Marco Fiorentino; et al. (ISSCC, 2015)

22.4 A 24Gb/s 0.71pJ/b Si-photonic source-synchronous receiver with adaptive equalization and microring wavelength stabilization. - Kunzhi Yu; Hao Li 047; Cheng Li; Alex Titriku; Ayman Shafik; Binhao Wang; Zhongkai Wang; Rui Bai 001; Chin-Hui Chen; Marco Fiorentino; Patrick Yin Chiang; Samuel Palermo (ISSCC, 2015)

Platform IO and system memory test using L3 cache based test (CBT) and parallel execution of CPGC Intel BIST engine. - Bruce Querbach; Tan Peter Yanyang; Lovelace Van; David Blankenbeckler; Rahul Khanna; Sudeep Puligundla; Patrick Chiang 001 (ITC, 2015)

Energy efficiency comparisons of NRZ and PAM4 modulation for ring-resonator-based silicon photonic links. - Binhao Wang; Kunzhi Yu; Hao Li 047; Patrick Yin Chiang; Samuel Palermo (MWSCAS, 2015)

A 25Gb/s, 520mW, 6.4Vpp Silicon-Photonic Mach-Zehnder Modulator with distributed driver in CMOS. - Nan Qi; Xianyao Li; Hao Li 047; Xi Xiao; Lei Wang 187; Zhiyong Li 014; Zhuo Gao; Yude Yu; Miki Moyal; Patrick Chiang 001 (OFC, 2015)

25Gb/s hybrid-integrated silicon photonic receiver with microring wavelength stabilization. - Kunzhi Yu; Chin-Hui Chen; Cheng Li; Hao Li 047; Alex Titriku; Binhao Wang; Ayman Shafik; Zhongkai Wang; Marco Fiorentino; Patrick Yin Chiang; Samuel Palermo (OFC, 2015)

A Micro-Power Two-Step Incremental Analog-to-Digital Converter. - Chia-Hung Chen; Yi Zhang 023; Tao He 001; Patrick Yin Chiang; Gabor C. Temes (IEEE J. Solid State Circuits, 2015)

A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS. - Hao Li 047; Zhe Xuan; Alex Titriku; Cheng Li; Kunzhi Yu; Binhao Wang; Ayman Shafik; Nan Qi; Yang Liu 178; Ran Ding; Tom Baehr Jones; Marco Fiorentino; et al. (IEEE J. Solid State Circuits, 2015)

Guest Editorial: Special Section on the 2014 IEEE Custom Integrated Circuits Conference (CICC 2014). - José M. de la Rosa 001; Patrick Chiang 001; Lawrence T. Clark (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A Framework for Compressive-Sensing of 3D Point Clouds. - Vahid Behravan; Gurjeet Singh; Patrick Yin Chiang (CIS, 2016)

21.6 A 1.2cm2 2.4GHz self-oscillating rectifier-antenna achieving -34.5dBm sensitivity for wirelessly powered sensors. - Jian Kang 007; Patrick Yin Chiang; Arun Natarajan 001 (ISSCC, 2016)

A 32Gb/s NRZ, 25GBaud/s PAM4 reconfigurable, Si-Photonic MZM transmitter in CMOS. - Nan Qi; Xi Xiao; Shang Hu; Miaofeng Li; Hao Li 047; Zhiyong Li 014; Patrick Chiang 001 (OFC, 2016)

Area-constrained wirelessly-powered UWB SoC design for small insect localization. - Jian Kang 007; Sujaya Rao; Patrick Chiang 001; Arun Natarajan 001 (WiSNet, 2016)

Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC. - Bruce Querbach; Rahul Khanna; Sudeep Puligundla; David Blankenbeckler; Joseph Crop; Patrick Yin Chiang (IEEE Des. Test, 2016)

Introduction to the Special Section on the 2015 Custom Integrated Circuits Conference. - Patrick Chiang 001; Visvesh S. Sathe 001 (IEEE J. Solid State Circuits, 2016)

A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization. - Kunzhi Yu; Cheng Li; Hao Li 047; Alex Titriku; Ayman Shafik; Binhao Wang; Zhongkai Wang; Rui Bai 001; Chin-Hui Chen; Marco Fiorentino; Patrick Yin Chiang; Samuel Palermo (IEEE J. Solid State Circuits, 2016)

Short-Range Low-Data-Rate FM-UWB Transceivers: Overview, Analysis, and Design. - Bo Zhou 004; Patrick Chiang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects. - Shuai Chen; Hao Li 047; Patrick Yin Chiang (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects. - Nan Qi; Yuhang Kang; Qipeng Lin; Jianxu Ma; Jingbo Shi; Bozhi Yin; Chang Liu; Rui Bai 001; Shang Hu; Juncheng Wang; Jiangbing Du; Lin Ma 008; et al. (A-SSCC, 2017)

A Mobile-Based High Sensitivity On-Field Organophosphorus Compounds Detecting System for IoT-Based Food Safety Tracking. - Han Jin; Yajie Qin; Hao Liang; Lei Wan; Hao Lan; Guoping Chen; Ran Liu 001; Li-Rong Zheng 001; Patrick Chiang 001; Zhiliang Hong (J. Sensors, 2017)

A Fully-Integrated 25Gb/s Low-Noise TIA+CDR Optical Receiver designed in 40nm-CMOS. - Juncheng Wang; Xuefeng Chen 004; Shang Hu; Yaxin Cai; Rui Bai 001; Xin Wang 130; Yuanxi Zhang; Shenglong Zhuo; Chang Liu; Bozhi Yin; Jianxu Ma; Hao Yan; et al. (A-SSCC, 2018)

A 50Gb/s-PAM4 CDR with On-Chip Eye Opening Monitor for Reference-Level and Clock-Sampling Adaptation. - Chang Liu; Bozhi Yin; Tingyu Yao; Nan Qi; Dan Li 011; Jingbo Shi; Juncheng Wang; Hu Shang; Rui Bai 001; Patrick Yin Chiang (OFC, 2018)

FotonNet: A HW-Efficient Object Detection System Using 3D-Depth Segmentation and 2D-DNN Classifier. - Gurjeet Singh; Sun Miao; Shi Shi; Patrick Chiang 001 (CoRR, 2018)

Deep Temporal Filter: An LSTM based approach to filter noise from TDC based SPAD Receiver. - Gurjeet Singh; Sun Miao; Patrick Chiang 001 (ISSPIT, 2019)

A 50Gb/s PAM-4 Retimer-CDR + VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die. - Shang Hu; Tingyu Yao; Bozhi Yin; Chunyu Song; Lei Zhao; Juncheng Wang; Lei Wang 187; Rui Bai 001; Xin Wang 130; Tao Xia; Yi Peng; Binbin Yao; et al. (OFC, 2019)

Low-Noise Broadband CMOS TIA Based on Multi-Stage Stagger-Tuned Amplifier for High-Speed High-Sensitivity Optical Communication. - Dan Li 011; Ming Liu 022; Shengwei Gao; Yongjun Shi; Yihua Zhang; Zhiyong Li 014; Patrick Yin Chiang; Franco Maloberti; Li Geng (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Fully Integrated 25 Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40-nm-CMOS. - Juncheng Wang; Quan Pan 002; Yajie Qin; Xuefeng Chen 004; Shang Hu; Rui Bai 001; Xin Wang 130; Yaxin Cai; Tao Xia; Yuanxi Zhang; Jianxu Ma; Nan Qi; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

FotonNet: A Hardware-efficient Object Detection System using 3D-depth Segmentation and 2D-deep Neural Network Classifier. - Gurjeet Singh; Sun Miao; Shi Shi; Patrick Chiang 001 (ICPRAM, 2020)

A 1.575GHz, 1.63mW CMOS Injection-Locked Ring Oscillator Powered by FBAR-Based PLL Reference. - Kangmin Hu; Julie R. Hu; Brian Otis; Patrick Yin Chiang (ISCAS, 2020)

A 112-Gb/s PAM-4 Linear Optical Receiver in 130-nm SiGe BiCMOS. - Dan Li 011; Shengwei Gao; Yongjun Shi; Xiaoyan Gui; Nan Qi; Zhiyong Li 014; Quan Pan 002; Patrick Chiang 001; Li Geng (ISCAS, 2020)

Anti-Gan: Discriminating 3D reconstructed and real faces for robust facial Identity in Anti-spoofing Generator Adversarial Network. - Miao Sun; Gurjeet Singh; Patrick Yin Chiang (ISSPIT, 2020)

PAM-X™: A 25Gb/s-PAM4 Optical Transceiver Chipset for 5G Optical Front-Haul. - Xin Wang 130; Yi Peng; Yuanxi Zhang; Tao Xia; Yifan Wu 009; Juncheng Wang; Lei Wang 187; Liujia Song; Lei Zhao; Shenglong Zhuo; Quan Pan 002; Xuefeng Chen 004; et al. (OFC, 2020)

A 50-Gb/s PAM4 Si-Photonic Transmitter With Digital-Assisted Distributed Driver and Integrated CDR in 40-nm CMOS. - Qiwen Liao; Nan Qi; Miaofeng Li; Shang Hu; Jian He; Bozhi Yin; Jingbo Shi; Jian Liu 021; Patrick Yin Chiang; Xi Xiao; Nanjian Wu (IEEE J. Solid State Circuits, 2020)

Energy-aware Retinaface: A Power Efficient Edge-Computing SOC for Face Detector in 40nm. - Miao Sun; Yingjie Cao; Patrick Yin Chiang (ASICON, 2021)

An integrated 8A pulsed VCSEL array driver under 12V supply with built-in pulse monitor and automatic peak current control for direct time-of-flight applications. - Tao Xia; Xuefeng Chen 004; Yuwei Wang; Yuan Li; Yifan Wu 009; Lei Wang 187; Liujia Song; Shenglong Zhuo; Zhihong Lin; Patrick Yin Chiang (A-SSCC, 2021)

A 4 × 10 Gb/s Adaptive Optical Receiver Utilizing Current-Reuse and Crosstalk-Remove. - Juncheng Wang; Xuefeng Chen 004; Rui Bai 001; Patrick Yin Chiang; Quan Pan 002 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20W/Ch Transmitter, and a 128x128 SPAD Receiver with SNR-Based Pixel Binning and Resolution Upscaling. - Shenglong Zhuo; Lei Zhao; Tao Xia; Lei Wang 187; Shi Shi; Yifan Wu 009; Chang Liu; Chill Wang; Yuwei Wang; Yuan Li; Hengwei Yu; Jiqing Xu; et al. (CICC, 2022)

An Integrated 200MHz 4A Pulsed Laser Driver with DLL-Based Time Interpolator for Indirect Time-of-Flight Applications. - Shenglong Zhuo; Yuwei Wang; Tao Xia; Yifan Wu 009; Lichun Xie; Wei Zheng; Zhihong Lin; Miao Sun; Lei Zhao; Yajie Qin; Rui Bai 001; Patrick Yin Chiang (ISCAS, 2022)

A 56-Gb/s Reconfigurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS. - Jian He; Yuguang Zhang; Han Liu; Qiwen Liao; Zhao Zhang 004; Miaofeng Li; Fan Jiang; Jingbo Shi; Jian Liu 021; Nanjian Wu; Yong Chen 005; Patrick Yin Chiang; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

An 8-A Sub-1ns Pulsed VCSEL Driver IC With Built-In Pulse Monitor and Automatic Peak Current Control for Direct Time-of-Flight Applications. - Tao Xia; Xuefeng Chen 004; Yifan Wu 009; Yuwei Wang; Yuan Li; Lei Wang 187; Liujia Song; Hengwei Yu; Jiqing Xu; Miao Sun; Jier Wang; Lei Zhao; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

dToF LIDAR System Using Addressable Multi-Channel VCSEL Transmitter, 128x80 SPAD Sensor, and ML-Based Object Detection for Adaptive Beam-Steering. - Yifan Wu 009; Sifan Zhou; Miao Sun; Tao Xia; Jian Qian; Lei Wang 187; Shi Shi; Lebei Cui; Chill Wang; Yuan Li; Hengwei Yu; Zhihong Lin; et al. (CICC, 2023)

A Sub-ns Pulsed VCSEL Driver with Real-Time Adaptive Current Control, Integrated Boost Switching Regulator and Class-1 Laser Eye Safety. - Tao Xia; Yuan Li; Liujia Song; Wei Chen; Hengwei Yu; Miao Sun; Lei Zhao; Zhihong Lin; Yuntong Tian; Hao Yan; Jiabin Meng; Yifan Wu 009; et al. (ESSCIRC, 2023)

A 2GHz On-Chip-Oscilloscope with High Accuracy Pulse Width Detection for Auto-Peak-Power Controller & Peak-Current Detector in Voltage-Mode DToF Driver. - Yuan Li; Zhihong Lin; Tao Xia; Jiqing Xu; Yuxiang Tang; Shenglong Zhuo; Xuefeng Chen 004; Xudong Zhang; Hengwei Yu; Huanli Jiang; Patrick Yin Chiang (ISCAS, 2023)

An Angle-Insensitive Time-Interleaved 4-Channels 138dB Dynamic Range Light Sensor with Flicker Detection for Smart Lighting Application. - Zhihong Lin; Yuan Li; Aaron Wang; Chill Wang; Qianfan Ran; Shenglong Zhuo; Yifan Wu 009; Hengwei Yu; Patrick Yin Chiang (ISCAS, 2023)

A 2KSPS 123dB Dynamic-Range SPAD-based Optical Sensor SoC with On-chip Auto-Gain-Control and FFT Processor for 100 μlux Light Illuminance and Flicker Detection. - Yifan Wu 009; Jier Wang; Hengwei Yu; Long Wang; Miao Sun; Zhihong Lin; Xiangyu Fang; Mengxin Yu; Jiqing Xu; Lei Qiu 002; Patrick Chiang 001; Shenglong Zhuo (ISCAS, 2023)

A Fully Integrated dToF System-on-Chip with High Precision Using Adaptive Optical Power Control and Shifted Histogram-Bin Binning. - Hengwei Yu; Shenglong Zhuo; Yifan Wu 009; Long Wang; Jiqing Xu; Jier Wang; Zhihong Lin; Patrick Yin Chiang (ISCAS, 2023)

FastPillars: A Deployment-friendly Pillar-based 3D Detector. - Sifan Zhou; Zhi Tian; Xiangxiang Chu; Xinyu Zhang 015; Bo Zhang 046; Xiaobo Lu; Chengjian Feng; Zequn Jie; Patrick Yin Chiang; Lin Ma 002 (CoRR, 2023)

Multi-Scale Histogram-Based Probabilistic Deep Neural Network for Super-Resolution 3D LiDAR Imaging. - Miao Sun; Shenglong Zhuo; Patrick Yin Chiang (Sensors, 2023)

A 200 MHz 14 W Pulsed Optical Illuminator With Laser Driver ASIC and On-Chip DLL-Based Time Interpolator for Indirect Time-of-Flight Applications. - Shenglong Zhuo; Yuwei Wang; Tao Xia; Yifan Wu 009; Wei Zheng; Miao Sun; Zhihong Lin; Patrick Yin Chiang (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20-W/Ch Transmitter, and a 128 × 128 SPAD Receiver With SNR-Based Pixel Binning and Resolution Upscaling. - Shenglong Zhuo; Tao Xia; Lei Zhao; Miao Sun; Yifan Wu 009; Lei Wang 187; Hengwei Yu; Jiqing Xu; Jier Wang; Zhihong Lin; Yuan Li; Lei Qiu 002; et al. (IEEE J. Solid State Circuits, 2023)

A dToF Ranging Sensor with Accurate Photon Detector Measurements for LiDAR Applications. - Hengwei Yu; Long Wang; Jiqing Xu; Patrick Yin Chiang (Sensors, 2023)

A 40nm 2TOPS/W Depth-Completion Neural Network Accelerator SoC With Efficient Depth Engine for Realtime LiDAR Systems. - Miao Sun; Yingjie Cao; Jian Qian; Jie Li; Sifan Zhou; Ziyu Zhao; Yifan Wu 009; Tao Xia; Yajie Qin; Lei Qiu 002; Shunli Ma; Patrick Yin Chiang; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 256 × 256 LiDAR Imaging System Based on a 200 mW SPAD-Based SoC with Microlens Array and Lightweight RGB-Guided Depth Completion Neural Network. - Jier Wang; Jie Li; Yifan Wu 009; Hengwei Yu; Lebei Cui; Miao Sun; Patrick Yin Chiang (Sensors, 2023)

Sub-SA: Strengthen In-Context Learning via Submodular Selective Annotation. - Jian Qian; Miao Sun; Sifan Zhou; Ziyu Zhao; Ruizhi Hun; Patrick Chiang 001 (ECAI, 2024)

7.5 A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE. - Xiongshi Luo; Xuewei You; Zhenghao Li; Hamed Mosalam; Dongfan Xu; Taiyang Fan; Hongchang Qiao; Wentao Zhou; Hongzhi Wu; Liping Zhong; Patrick Yin Chiang; Quan Pan 002 (ISSCC, 2024)

TimeLDM: Latent Diffusion Model for Unconditional Time Series Generation. - Jian Qian; Miao Sun; Sifan Zhou; Biao Wan; Minhao Li; Patrick Chiang 001 (CoRR, 2024)

SDformer: Efficient End-to-End Transformer for Depth Completion. - Jian Qian; Miao Sun; Ashley Lee; Jie Li; Shenglong Zhuo; Patrick Yin Chiang (CoRR, 2024)

An Angle-Insensitive 138-dB Dynamic Range Light Sensor With 4 Time-Interleaved Channels 32-ppm/°C Temperature-Independent Flicker Detection. - Yuan Li; Zhihong Lin; Wenbo Dong; Ziwen Hu; Chill Wang; Shenglong Zhuo; Yifan Wu 009; Hengwei Yu; Patrick Yin Chiang (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

The Photoacoustic Quality-Enhancement Neural Network Processor with the Scalable and End-to-End Architecture by Improving the Sparsity Level. - Miao Sun; Zhengyuan Zhang; Jie Ma; Caijie Liang; Boyi Dong; Yange Wang; Zhongzhiguang Lu; Yahui Li; Xiangjun Yin; Shenglong Zhuo; Yifan Wu 009; Yingjie Cao; et al. (ISCAS, 2025)

A depth-aware geometric fusion based view synthesis method for sparse RGB-D input. - Ziyu Zhao; Xiaobo Lu; Sifan Zhou; Patrick Yin Chiang (Expert Syst. Appl., 2025)

BioMamba: Leveraging Spectro-Temporal Embedding in Bidirectional Mamba for Enhanced Biosignal Classification. - Jian Qian; Teck Lun Goh; Bingyu Xie; Chengyao Zhu; Biao Wan; Yawen Guan; Rachel Ding Chen; Patrick Yin Chiang (CoRR, 2025)

An Adaptive Beam-Steering dToF LiDAR System Using Addressable Multi-Channel VCSEL Transmitter, 128 × 80 SPAD Sensor, and ML-Based Edge-Computing Object Detection. - Yifan Wu 009; Miao Sun; Sifan Zhou; Tao Xia; Lei Wang 187; Jier Wang; Yuan Li; Ming Zhong; Rui Bai 001; Xuefeng Chen 004; Yuanjin Zheng; Patrick Yin Chiang; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Sub-Nanosecond Pulsed VCSEL Driver With PVT-Compensated Constant Current, Integrated Boost Switching Regulator and Class-1 Laser Eye Safety. - Ming Zhong; Yifan Wu 009; Yuan Li; Wei Chen; Miao Sun; Liujia Song; Shanyu Cui; Xuefeng Chen 004; Patrick Yin Chiang; Shenglong Zhuo; Tao Xia (IEEE J. Solid State Circuits, 2025)