Patrick Chiang

According to our database1, Patrick Chiang authored at least 83 papers between 2001 and 2018.

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Bibliography

2018
FotonNet: A HW-Efficient Object Detection System Using 3D-Depth Segmentation and 2D-DNN Classifier.
CoRR, 2018

A Fully-Integrated 25Gb/s Low-Noise TIA+CDR Optical Receiver designed in 40nm-CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A Mobile-Based High Sensitivity On-Field Organophosphorus Compounds Detecting System for IoT-Based Food Safety Tracking.
J. Sensors, 2017

A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects.
IEEE Trans. VLSI Syst., 2016

Short-Range Low-Data-Rate FM-UWB Transceivers: Overview, Analysis, and Design.
IEEE Trans. on Circuits and Systems, 2016

A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization.
J. Solid-State Circuits, 2016

Introduction to the Special Section on the 2015 Custom Integrated Circuits Conference.
J. Solid-State Circuits, 2016

Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC.
IEEE Design & Test, 2016

21.6 A 1.2cm2 2.4GHz self-oscillating rectifier-antenna achieving -34.5dBm sensitivity for wirelessly powered sensors.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A Framework for Compressive-Sensing of 3D Point Clouds.
Proceedings of the 12th International Conference on Computational Intelligence and Security, 2016

2015
Guest Editorial: Special Section on the 2014 IEEE Custom Integrated Circuits Conference (CICC 2014).
IEEE Trans. on Circuits and Systems, 2015

A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS.
J. Solid-State Circuits, 2015

A Micro-Power Two-Step Incremental Analog-to-Digital Converter.
J. Solid-State Circuits, 2015

Platform IO and system memory test using L3 cache based test (CBT) and parallel execution of CPGC Intel BIST engine.
Proceedings of the 2015 IEEE International Test Conference, 2015

22.4 A 24Gb/s 0.71pJ/b Si-photonic source-synchronous receiver with adaptive equalization and microring wavelength stabilization.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

22.6 A 25Gb/s 4.4V-swing AC-coupled Si-photonic microring transmitter with 2-tap asymmetric FFE and dynamic thermal tuning in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A compressed-sensing sensor-on-chip incorporating statistics collection to improve reconstruction performance.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

Rate-adaptive compressed-sensing and sparsity variance of biomedical signals.
Proceedings of the 12th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2015

A 20 μW dual-channel analog front-end in 65nm CMOS for portable ECG monitoring system.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
0.56 V, -20 dBm RF-Powered, Multi-Node Wireless Body Area Network System-on-a-Chip With Harvesting-Efficiency Tracking Loop.
J. Solid-State Circuits, 2014

An 8-16 Gb/s, 0.65-1.05 pJ/b, Voltage-Mode Transmitter With Analog Impedance Modulation Equalization and Sub-3 ns Power-State Transitioning.
J. Solid-State Circuits, 2014

Silicon Photonic Transceiver Circuits With Microring Resonator Bias-Based Wavelength Stabilization in 65 nm CMOS.
J. Solid-State Circuits, 2014

A Low-Power, Low-Voltage WBAN-Compatible Sub-Sampling PSK Receiver in 65 nm CMOS.
J. Solid-State Circuits, 2014

A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

A reusable BIST with software assisted repair technology for improved memory and IO debug, validation and test time.
Proceedings of the 2014 International Test Conference, 2014

A 41-mW 30-Gb/s CMOS optical receiver with digitally-tunable cascaded equalization.
Proceedings of the ESSCIRC 2014, 2014

A piezoelectric energy-harvesting shoe system for podiatric sensing.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

Energy-efficient bio-sensing systems.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A 11μW 250 Hz BW two-step incremental ADC with 100 dB DR and 91 dB SNDR for integrated sensor interfaces.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects.
IEEE Trans. VLSI Syst., 2013

A Near-Threshold, 0.16 nJ/b OOK-Transmitter With 0.18 nJ/b Noise-Cancelling Super-Regenerative Receiver for the Medical Implant Communications Service.
IEEE Trans. Biomed. Circuits and Systems, 2013

A 0.47-0.66 pJ/bit, 4.8-8 Gb/s I/O Transceiver in 65 nm CMOS.
J. Solid-State Circuits, 2013

A ring-resonator-based silicon photonics transceiver with bias-based wavelength stabilization and adaptive-power-sensitivity receiver.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

High-sensitivity photodetection sensor front-end, detecting organophosphourous compounds for food safety.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Area-Efficient Antenna-Scalable MIMO Detector for K-best Sphere Decoding.
Signal Processing Systems, 2012

A Comparative Study of 20-Gb/s NRZ and Duobinary Signaling Using Statistical Analysis.
IEEE Trans. VLSI Syst., 2012

Power-Scalable, Complex Bandpass/Low-Pass Filter With I/Q Imbalance Calibration for a Multimode GNSS Receiver.
IEEE Trans. on Circuits and Systems, 2012

Sub-2-ps, Static Phase Error Calibration Technique Incorporating Measurement Uncertainty Cancellation for Multi-Gigahertz Time-Interleaved T/H Circuits.
IEEE Trans. on Circuits and Systems, 2012

A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration.
IEEE Trans. on Circuits and Systems, 2012

A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS.
J. Solid-State Circuits, 2012

0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking.
J. Solid-State Circuits, 2012

A low-power, capacitively-divided, ring oscillator with digitally adjustable voltage swing.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Innovative approach to server performance and power monitoring in data centers using wireless sensors (invited paper).
Proceedings of the 2012 IEEE Radio and Wireless Symposium, 2012

A 530mV 10-lane SIMD processor with variation resiliency in 45nm SOI.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Register file write data gating techniques and break-even analysis model.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

A low-leakage dynamic register file with unclocked wordline and sub-segmentation for improved bitline scalability.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

A 12-bit 7 µW/channel 1 kHz/channel incremental ADC for biosensor interface circuits.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Location and activity tracking with the cloud.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

125Mbps ultra-wideband system evaluation for cortical implant devices.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

Regaining throughput using completion detection for error-resilient, near-threshold logic.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

A near-threshold, multi-node, wireless body area sensor network powered by RF energy harvesting.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
Sinusoidal Clock Sampling for Multigigahertz ADCs.
IEEE Trans. on Circuits and Systems, 2011

A 90 nm-CMOS, 500 Mbps, 3-5 GHz Fully-Integrated IR-UWB Transceiver With Multipath Equalization Using Pulse Injection-Locking for Receiver Phase Synchronization.
J. Solid-State Circuits, 2011

Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links.
J. Electrical and Computer Engineering, 2011

100-phase, dual-loop delay-locked loop for impulse radio ultra-wideband coherent receiver synchronisation.
IET Circuits, Devices & Systems, 2011

Experimental Characterization of a UWB Channel for Body Area Networks.
EURASIP J. Wireless Comm. and Networking, 2011

Network coding in multicore processors.
Proceedings of the 30th IEEE International Performance Computing and Communications Conference, 2011

Design automation methodology for improving the variability of synthesized digital circuits operating in the sub/near-threshold regime.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Indoor localization using pedestrian dead reckoning updated with RFID-based fiducials.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

An energy-efficient 64-QAM MIMO detector for emerging wireless standards.
Proceedings of the Design, Automation and Test in Europe, 2011

Energy-efficient transceiver circuits for short-range on-chip interconnects.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOS.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

All-digital 3-50 GHz ultra-wideband pulse generator for short-range wireless interconnect in 40nm CMOS.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
Chaotic Pulse-Position Baseband Modulation for an Ultra-Wideband Transceiver in CMOS.
IEEE Trans. on Circuits and Systems, 2010

A 0.6 mW/Gb/s, 6.4-7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS.
J. Solid-State Circuits, 2010

Short-Range, Wireless Interconnect within a Computing Chassis: Design Challenges.
IEEE Design & Test of Computers, 2010

Synctium: a Near-Threshold Stream Processor for Energy-Constrained Parallel Applications.
Computer Architecture Letters, 2010

SWIFT: A SWing-reduced interconnect for a Token-based Network-on-Chip in 90nm CMOS.
Proceedings of the 28th International Conference on Computer Design, 2010

Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
A Fast-Settling Wideband-IF ASK Baseband Circuit for a Wireless Endoscope Capsule.
IEEE Trans. on Circuits and Systems, 2009

A 0.18-muhboxm CMOS GFSK Analog Front End Using a Bessel-Based Quadrature Discriminator With On-Chip Automatic Tuning.
IEEE Trans. on Circuits and Systems, 2009

Express Virtual Channels with Capacitively Driven Global Links.
IEEE Micro, 2009

Measuring and Compensating for Process Mismatch-induced, Reference Spurs in Phase-locked Loops using a Sub-sampled DSP.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Sense Amplifier Power and Delay Characterization for Operation under Low-Vdd and Low-voltage Clock Swing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Comparison of On-die Global Clock Distribution Methods for Parallel Serial Links.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A 10Gb/s Wire-line Transceiver with Half Rate Period Calibration CDR.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication.
Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008

2007
Process Variation Compensation of a 2.4GHz LNA in 0.18um CMOS Using Digitally Switchable Capacitance.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2001
Monolithic chaotic communications system.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001


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