A Novel Approach to Delay-Fault Diagnosis. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (DAC, 1992)

A New Reliable Method for Delay-Fault Diagnosis. - Marie-Lise Flottes; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (VLSI Design, 1992)

Delay-Fault Diagnosis by Critical-Path Tracing. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (IEEE Des. Test Comput., 1992)

An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation. - D. Dumas; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (ITC, 1993)

Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. - D. Dumas; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (EDAC-ETC-EUROASIC, 1994)

A trace-based method for delay fault diagnosis in synchronous sequential circuits. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; B. Rodriguez (ED&TC, 1995)

Diagnostic of path and gate delay faults in non-scan sequential circuits. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; B. Rodriguez (VTS, 1995)

An advanced diagnostic method for delay faults in combinational faulty circuits. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (J. Electron. Test., 1995)

Delay fault diagnosis in sequential circuits based on path tracing. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; B. Rodriguez (Integr., 1995)

DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits. - P. Cavallera; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (ED&TC, 1996)

A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; B. Rodriguez (ITC, 1996)

A new test pattern generation method for delay fault testing. - S. Cremoux; Christophe Fagot; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (VTS, 1996)

A gate resizing technique for high reduction in power consumption. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; D. Severac (ISLPED, 1997)

On Using Machine Learning for Logic BIST. - Christophe Fagot; Patrick Girard 001; Christian Landrault (ITC, 1997)

An optimized BIST test pattern generator for delay testing. - Patrick Girard 001; Christian Landrault; V. Moreda; Serge Pravossoudovitch (VTS, 1997)

A non-iterative gate resizing algorithm for high reduction in power consumption. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; D. Severac (Integr., 1997)

A BIST Structure to Test Delay Faults in a Scan Environment. - Patrick Girard 001; Christian Landrault; V. Moreda; Serge Pravossoudovitch; Arnaud Virazel (Asian Test Symposium, 1998)

Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (Asian Test Symposium, 1999)

GIPSE, A Model-Based System for CAD Software. - Guillaume Patry; Patrick Girard 001 (CADUI, 1999)

On calculating efficient LFSR seeds for built-in self test. - Christophe Fagot; Olivier Gascuel; Patrick Girard 001; Christian Landrault (ETW, 1999)

A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (Great Lakes Symposium on VLSI, 1999)

Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; Joan Figueras; Salvador Manich; João Paulo Teixeira 001; Marcelino B. Santos (ISCAS (1), 1999)

A Test Vector Inhibiting Technique for Low Energy BIST Design. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (VTS, 1999)

A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. - Patrick Girard 001; Christian Landrault; V. Moreda; Serge Pravossoudovitch; Arnaud Virazel (J. Electron. Test., 1999)

An adjacency-based test pattern generator for low power BIST design. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (Asian Test Symposium, 2000)

Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (IOLTW, 2000)

Low Power Testing of VLSI Circuits: Problems and Solutions. - Patrick Girard 001 (ISQED, 2000)

Low power BIST design by hypergraph partitioning: methodology and architectures. - Patrick Girard 001; Christian Landrault; Loïs Guiller; Serge Pravossoudovitch (ITC, 2000)

Hidden Markov and Independence Models with Patterns for Sequential BIST. - Laurent Bréhélin; Olivier Gascuel; Gilles Caraux; Patrick Girard 001; Christian Landrault (VTS, 2000)

Low Power BIST by Filtering Non-Detecting Vectors. - Salvador Manich; A. Gabarró; M. Lopez; Joan Figueras; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; João Paulo Teixeira 001; Marcelino B. Santos (J. Electron. Test., 2000)

A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (Asian Test Symposium, 2001)

Random Adjacent Sequences: An Efficient Solution for Logic BIST. - René David; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (VLSI-SOC, 2001)

A Gated Clock Scheme for Low Power Scan-Based BIST. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (IOLTW, 2001)

End-User Programming in a Structured Dialogue Environment: the GIPSE Project. - Guillaume Patry; Patrick Girard 001 (HCC, 2001)

A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; Hans-Joachim Wunderlich (VTS, 2001)

Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences. - Arnaud Virazel; René David; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (J. Electron. Test., 2001)

Test Power: a Big Issue in Large SOC Designs. - Yannick Bonhomme; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (DELTA, 2002)

Power Driven Chaining of Flip-Flops in Scan Architectures. - Yannick Bonhomme; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (ITC, 2002)

On Using Efficient Test Sequences for BIST. - René David; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (VTS, 2002)

Survey of Low-Power Testing of VLSI Circuits. - Patrick Girard 001 (IEEE Des. Test Comput., 2002)

High Defect Coverage with Low-Power Test Sequences in a BIST Environment. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel; Hans-Joachim Wunderlich (IEEE Des. Test Comput., 2002)

Hardware Generation of Random Single Input Change Test Sequences. - René David; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (J. Electron. Test., 2002)

Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Simone Borri (Asian Test Symposium, 2003)

Defect-oriented dynamic fault models for embedded-SRAMs. - Simone Borri; Magali Hage-Hassan; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel (ETW, 2003)

Requirements for delay testing of look-up tables in SRAM-based FPGAs. - Patrick Girard 001; Olivier Héron; Serge Pravossoudovitch; Michel Renovell (ETW, 2003)

Defect Analysis for Delay-Fault BIST in FPGAs. - Patrick Girard 001; Olivier Héron; Serge Pravossoudovitch; Michel Renovell (IOLTS, 2003)

Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (ITC, 2003)

A Ring Architecture Strategy for BIST Test Pattern Generation. - Christophe Fagot; Olivier Gascuel; Patrick Girard 001; Christian Landrault (J. Electron. Test., 2003)

Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Simone Borri; Magali Bastian Hage-Hassan (Asian Test Symposium, 2004)

Design of Routing-Constrained Low Power Scan Chains. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (DELTA, 2004)

High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. - Patrick Girard 001; Olivier Héron; Serge Pravossoudovitch; Michel Renovell (DELTA, 2004)

An efficient scan tree design for test time reduction. - Yannick Bonhomme; Tomokazu Yoneda; Hideo Fujiwara; Patrick Girard 001 (ETS, 2004)

Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Simone Borri; Magali Bastian Hage-Hassan (ETS, 2004)

Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs. - Patrick Girard 001; Olivier Héron; Serge Pravossoudovitch; Michel Renovell (ETS, 2004)

BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. - Patrick Girard 001; Olivier Héron; Serge Pravossoudovitch; Michel Renovell (IOLTS, 2004)

SUIDT: safe user interface design tool. - Mickaël Baron; Patrick Girard 001 (IUI, 2004)

March iC-: An Improved Version of March C- for ADOFs Detection. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Simone Borri (VTS, 2004)

Power-Driven Routing-Constrained Scan Chain Design. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (J. Electron. Test., 2004)

Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian (DAC, 2005)

Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian Hage-Hassan (ETS, 2005)

Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. - Nabil Badereddine; Patrick Girard 001; Arnaud Virazel; Serge Pravossoudovitch; Christian Landrault (PATMOS, 2005)

Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. - Nabil Badereddine; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Christian Landrault (VLSI-SoC, 2005)

Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian Hage-Hassan (VTS, 2005)

Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. - Simone Borri; Magali Hage-Hassan; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel (J. Electron. Test., 2005)

Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Simone Borri; Magali Hage-Hassan (J. Electron. Test., 2005)

Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. - Patrick Girard 001; Olivier Héron; Serge Pravossoudovitch; Michel Renovell (J. Electron. Test., 2005)

Welcome to the Journal of Low Power Electronics. - Patrick Girard 001 (J. Low Power Electron., 2005)

Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing. - Patrick Girard 001; Yannick Bonhomme (J. Low Power Electron., 2005)

Power-Aware Test Data Compression for Embedded IP Cores. - Nabil Badereddine; Zhanglei Wang; Patrick Girard 001; Krishnendu Chakrabarty; Serge Pravossoudovitch; Christian Landrault (ATS, 2006)

Minimizing test power in SRAM through reduction of pre-charge activity. - Luigi Dilillo; Paul M. Rosinger; Bashir M. Al-Hashimi; Patrick Girard 001 (DATE, 2006)

March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian (DDECS, 2006)

Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. - Nabil Badereddine; Patrick Girard 001; Serge Pravossoudovitch; Christian Landrault; Arnaud Virazel; Hans-Joachim Wunderlich (VLSI-SoC, 2006)

An Overview of Failure Mechanisms in Embedded Flash Memories. - Olivier Ginez; Jean Michel Daga; Marylene Combe; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (VTS, 2006)

A Gated Clock Scheme for Low Power Testing of Logic Cores. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (J. Electron. Test., 2006)

ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Simone Borri; Magali Bastian Hage-Hassan (J. Electron. Test., 2006)

An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. - Patrick Girard 001; Olivier Héron; Serge Pravossoudovitch; Michel Renovell (J. Electron. Test., 2006)

Reducing Power Dissipation in SRAM during Test. - Luigi Dilillo; Paul M. Rosinger; Bashir M. Al-Hashimi; Patrick Girard 001 (J. Low Power Electron., 2006)

Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior. - Magali Bastian; Vincent Gouin; Patrick Girard 001; Christian Landrault; Alexandre Ney; Serge Pravossoudovitch; Arnaud Virazel (ATS, 2007)

Fast Bridging Fault Diagnosis using Logic Information. - Alexandre Rousset; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (ATS, 2007)

Slow write driver faults in 65nm SRAM technology: analysis and March test solution. - Alexandre Ney; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian (DATE, 2007)

A Mixed Approach for Unified Logic Diagnosis. - Alexandre Rousset; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (DDECS, 2007)

Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. - Olivier Ginez; Jean Michel Daga; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (ETS, 2007)

Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. - Alexandre Ney; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian (ETS, 2007)

DERRIC: A Tool for Unified Logic Diagnosis. - Alexandre Rousset; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (ETS, 2007)

A concurrent approach for testing address decoder faults in eFlash memories. - Olivier Ginez; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel; Jean Michel Daga (ITC, 2007)

A novel scheme to reduce power supply noise for high-quality at-speed scan testing. - Xiaoqing Wen; Kohei Miyase; Seiji Kajihara; Tatsuya Suzuki; Yuta Yamato; Patrick Girard 001; Yuji Ohsumi; Laung-Terng Wang (ITC, 2007)

Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. - Olivier Ginez; Jean Michel Daga; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (VTS, 2007)

Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. - Alexandre Ney; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian (VTS, 2007)

Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian (J. Electron. Test., 2007)

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing. - Hiroshi Furukawa; Xiaoqing Wen; Kohei Miyase; Yuta Yamato; Seiji Kajihara; Patrick Girard 001; Laung-Terng Wang; Mohammad Tehranipoor (ATS, 2008)

Power-Aware Testing and Test Strategies for Low Power Devices. - Dimitris Gizopoulos; Kaushik Roy 001; Patrick Girard 001; Nicola Nicolici; Xiaoqing Wen (DATE, 2008)

A Design-for-Diagnosis Technique for SRAM Write Drivers. - Alexandre Ney; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian; Vincent Gouin (DATE, 2008)

SoC Symbolic Simulation: a case study on delay fault testing. - Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Paolo Bernardi (DDECS, 2008)

Improving Diagnosis Resolution without Physical Information. - Alexandre Rousset; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (DELTA, 2008)

Using TMR Architectures for Yield Improvement. - Julien Vial; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (DFT, 2008)

Yield Improvement, Fault-Tolerance to the Rescue?. - Julien Vial; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (IOLTS, 2008)

A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs. - Alexandre Ney; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian (ITC, 2008)

SoC Yield Improvement: Redundant Architectures to the Rescue? - Julien Vial; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (ITC, 2008)

An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing. - Alexandre Ney; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian; Vincent Gouin (VTS, 2008)

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction. - Nabil Badereddine; Zhanglei Wang; Patrick Girard 001; Krishnendu Chakrabarty; Arnaud Virazel; Serge Pravossoudovitch; Christian Landrault (J. Electron. Test., 2008)

Guest Editorial. - Nicola Nicolici; Patrick Girard 001 (J. Electron. Test., 2008)

Delay Fault Diagnosis in Sequential Circuits. - Youssef Benabboud; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Olivia Riewer (Asian Test Symposium, 2009)

A new design-for-test technique for SRAM core-cell stability faults. - Alexandre Ney; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian; Vincent Gouin (DATE, 2009)

Comprehensive bridging fault diagnosis based on the SLAT paradigm. - Youssef Benabboud; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Laroussi Bouzaida; Isabelle Izaute (DDECS, 2009)

An efficient fault simulation technique for transition faults in non-scan sequential circuits. - Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Paolo Bernardi; Matteo Sonza Reorda (DDECS, 2009)

A case study on logic diagnosis for System-on-Chip. - Youssef Benabboud; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Laroussi Bouzaida; Isabelle Izaute (ISQED, 2009)

NAND flash testing: A preliminary study on actual defects. - Pierre-Didier Mauroux; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Benoît Godard (ITC, 2009)

A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash. - Olivier Ginez; Jean Michel Daga; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (J. Electron. Test., 2009)

Is triple modular redundancy suitable for yield improvement? - Julien Vial; Arnaud Virazel; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (IET Comput. Digit. Tech., 2009)

Analysis of Resistive-Open Defects in SRAM Sense Amplifiers. - Alexandre Ney; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A Comprehensive System-on-Chip Logic Diagnosis. - Youssef Benabboud; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Olivia Riewer (Asian Test Symposium, 2010)

A Memory Fault Simulator for Radiation-Induced Effects in SRAMs. - Paolo Rech; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Luigi Dilillo (Asian Test Symposium, 2010)

A statistical simulation method for reliability analysis of SRAM core-cells. - Renan Alves Fonseca; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Nabil Badereddine (DAC, 2010)

Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes. - Fangmei Wu; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Junxia Ma; Wei Zhao 010; Mohammad Tehranipoor; Xiaoqing Wen (DDECS, 2010)

An Exact and Efficient Critical Path Tracing Algorithm. - Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Paolo Bernardi; Matteo Sonza Reorda (DELTA, 2010)

Impact of Resistive-Bridging Defects in SRAM Core-Cell. - Renan Alves Fonseca; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Nabil Badereddine (DELTA, 2010)

Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. - Renan Alves Fonseca; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Nabil Badereddine (ETS, 2010)

Setting test conditions for improving SRAM reliability. - Renan Alves Fonseca; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Nabil Badereddine (ETS, 2010)

A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction. - Pierre-Didier Mauroux; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Benoît Godard; Gilles Festes; Laurent Vachez (ETS, 2010)

Pattern grading for testing critical paths considering power supply noise and crosstalk using a layout-aware quality metric. - Junxia Ma; Jeremy Lee; Mohammad Tehranipoor; Nisar Ahmed; Patrick Girard 001 (ACM Great Lakes Symposium on VLSI, 2010)

A roaming memory test bench for detecting particle induced SEUs. - Jean-Marc Gallière; Paolo Rech; Patrick Girard 001; Luigi Dilillo (ITC, 2010)

Parity prediction synthesis for nano-electronic gate designs. - D. A. Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Hans-Joachim Wunderlich (ITC, 2010)

Is test power reduction through X-filling good enough? - Fangmei Wu; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Mohammad Tehranipoor; Kohei Miyase; Xiaoqing Wen; Nisar Ahmed (ITC, 2010)

Detecting NBTI induced failures in SRAM core-cells. - Renan Alves Fonseca; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Nabil Badereddine (VTS, 2010)

High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme. - Kohei Miyase; Xiaoqing Wen; Hiroshi Furukawa; Yuta Yamato; Seiji Kajihara; Patrick Girard 001; Laung-Terng Wang; Mohammad Tehranipoor (IEICE Trans. Inf. Syst., 2010)

A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes. - Fangmei Wu; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Mohammad Tehranipoor; Xiaoqing Wen; Nisar Ahmed (J. Low Power Electron., 2010)

A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects. - Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel (IEEE Trans. Computers, 2010)

Power-Aware Test Pattern Generation for At-Speed LOS Testing. - Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri; Arnaud Virazel; Kohei Miyase; Xiaoqing Wen (Asian Test Symposium, 2011)

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. - Kohei Miyase; Y. Uchinodan; Kazunari Enokimoto; Yuta Yamato; Xiaoqing Wen; Seiji Kajihara; Fangmei Wu; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Arnaud Virazel (Asian Test Symposium, 2011)

A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. - D. A. Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Hans-Joachim Wunderlich (Asian Test Symposium, 2011)

Failure Analysis and Test Solutions for Low-Power SRAMs. - Leonardo Bonet Zordan; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Aida Todri; Arnaud Virazel; Nabil Badereddine (Asian Test Symposium, 2011)

On using a SPICE-like TSTAC™ eFlash model for design and test. - Pierre-Didier Mauroux; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Benoît Godard; Gilles Festes; Laurent Vachez (DDECS, 2011)

A study of path delay variations in the presence of uncorrelated power and ground supply noise. - Aida Todri; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel (DDECS, 2011)

Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling. - Leonardo Bonet Zordan; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Nabil Badereddine (DDECS, 2011)

On the Modeling of Gate Delay Faults by Means of Transition Delay Faults. - Paolo Bernardi; Matteo Sonza Reorda; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch (DFT, 2011)

Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector. - Luigi Dilillo; Alberto Bosio; Miroslav Valka; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel (DFT, 2011)

A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. - Miroslav Valka; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Ernesto Sánchez 001; Mauricio de Carvalho; Matteo Sonza Reorda (ETS, 2011)

On using address scrambling to implement defect tolerance in SRAMs. - Renan Alves Fonseca; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Nabil Badereddine (ITC, 2011)

Neutron detection in atmospheric environment through static and dynamic SRAM-based test bench. - Luigi Dilillo; Paolo Rech; Jean-Marc Gallière; Patrick Girard 001; Frederic Wrobel; Frédéric Saigné (LATW, 2011)

Power-aware test generation with guaranteed launch safety for at-speed scan testing. - Xiaoqing Wen; Kazunari Enokimoto; Kohei Miyase; Yuta Yamato; Michael A. Kochte; Seiji Kajihara; Patrick Girard 001; Mohammad Tehranipoor (VTS, 2011)

Impact of Resistive-Bridge Defects in TAS-MRAM Architectures. - Joao Azevedo; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri; Guillaume Prenat; Jérémy Alvarez-Herault; Ken Mackay (Asian Test Symposium, 2012)

Peak Power Estimation: A Case Study on CPU Cores. - Paolo Bernardi; Mauricio de Carvalho; Ernesto Sánchez 001; Matteo Sonza Reorda; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Miroslav Valka (Asian Test Symposium, 2012)

Why and How Controlling Power Consumption during Test: A Survey. - Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri; Arnaud Virazel (Asian Test Symposium, 2012)

Power Supply Noise Sensor Based on Timing Uncertainty Measurements. - Miroslav Valka; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri; Arnaud Virazel; P. Debaud; S. Guilhot (Asian Test Symposium, 2012)

Impact of resistive-open defects on the heat current of TAS-MRAM architectures. - Joao Azevedo; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri-Sanial; Guillaume Prenat; Jérémy Alvarez-Herault; Ken Mackay (DATE, 2012)

Coupling-based resistive-open defects in TAS-MRAM architectures. - Joao Azevedo; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri; Guillaume Prenat; Jérémy Alvarez-Herault; Ken Mackay (ETS, 2012)

Through-Silicon-Via resistive-open defect analysis. - Carolina Metzler; Aida Todri; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Arnaud Virazel (ETS, 2012)

Defect analysis in power mode control logic of low-power SRAMs. - Leonardo Bonet Zordan; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri; Arnaud Virazel; Nabil Badereddine (ETS, 2012)

Evaluation of test algorithms stress effect on SRAMs under neutron radiation. - Georgios Tsiligiannis; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Aida Todri; Arnaud Virazel; Antoine D. Touboul; Frederic Wrobel; Frédéric Saigné (IOLTS, 2012)

On pinpoint capture power management in at-speed scan test generation. - Xiaoqing Wen; Y. Nishida; Kohei Miyase; Seiji Kajihara; Patrick Girard 001; Mohammad Tehranipoor; Laung-Terng Wang (ITC, 2012)

Low-power SRAMs power mode control logic: Failure analysis and test solutions. - Leonardo Bonet Zordan; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri; Arnaud Virazel; Nabil Badereddine (ITC, 2012)

Advanced test methods for SRAMs. - Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel (VTS, 2012)

A pseudo-dynamic comparator for error detection in fault tolerant architectures. - D. A. Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri; Michael E. Imhof; Hans-Joachim Wunderlich (VTS, 2012)

Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes. - Renan Alves Fonseca; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Nabil Badereddine (J. Electron. Test., 2012)

A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk. - Junxia Ma; Mohammad Tehranipoor; Patrick Girard 001 (J. Electron. Test., 2012)

Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTACTM eFlash Memories. - Pierre-Didier Mauroux; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Benoît Godard; Gilles Festes; Laurent Vachez (J. Electron. Test., 2012)

Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns. - Hassan Salmani; Wei Zhao 010; Mohammad Tehranipoor; Sreejit Chakravarty; Patrick Girard 001; Xiaoqing Wen (J. Low Power Electron., 2012)

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. - Akihiro Tomita; Xiaoqing Wen; Yasuo Sato; Seiji Kajihara; Patrick Girard 001; Mohammad Tehranipoor; Laung-Terng Wang (Asian Test Symposium, 2013)

Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing. - Elena I. Vatajelu; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Aida Todri; Arnaud Virazel; Nabil Badereddine (Asian Test Symposium, 2013)

Test solution for data retention faults in low-power SRAMs. - Leonardo Bonet Zordan; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri; Arnaud Virazel; Nabil Badereddine (DATE, 2013)

On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell. - Elena I. Vatajelu; Georgios Tsiligiannis; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Aida Todri; Arnaud Virazel; Frederic Wrobel; Frédéric Saigné (DFTS, 2013)

Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures. - Elena I. Vatajelu; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri; Arnaud Virazel; Nabil Badereddine (DTIS, 2013)

Computing detection probability of delay defects in signal line tsvs. - Carolina Metzler; Aida Todri-Sanial; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Arnaud Virazel; Pascal Vivet; Marc Belleville (ETS, 2013)

Analyzing resistive-open defects in SRAM core-cell under the effect of process variability. - Elena I. Vatajelu; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri; Arnaud Virazel; Nabil Badereddine (ETS, 2013)

SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations. - Georgios Tsiligiannis; Elena I. Vatajelu; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Aida Todri; Arnaud Virazel; Frederic Wrobel; Frédéric Saigné (IOLTS, 2013)

Effect-cause intra-cell diagnosis at transistor level. - Zhenzhou Sun; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri; Arnaud Virazel; Etienne Auvray (ISQED, 2013)

A novel method to mitigate TSV electromigration for 3D ICs. - Yuanqing Cheng; Aida Todri-Sanial; Alberto Bosio; Luigi Dillio; Patrick Girard 001; Arnaud Virazel; Pascal Vivet; Marc Belleville (ISVLSI, 2013)

On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs. - Leonardo Bonet Zordan; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri; Arnaud Virazel; Nabil Badereddine (ITC, 2013)

Characterization of an SRAM based particle detector for mixed-field radiation environments. - Georgios Tsiligiannis; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Aida Todri-Sanial; Arnaud Virazel; Julien Mekki; Markus Brugger; J.-R. Vaillé; Frederic Wrobel; Frédéric Saigné (IWASI, 2013)

Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains. - Aida Todri-Sanial; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel (NEWCAS, 2013)

A built-in scheme for testing and repairing voltage regulators of low-power srams. - Leonardo Bonet Zordan; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri; Arnaud Virazel; Nabil Badereddine (VTS, 2013)

Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption. - Paolo Bernardi; Mauricio de Carvalho; Ernesto Sánchez 001; Matteo Sonza Reorda; Alberto Bosio; Luigi Dilillo; Miroslav Valka; Patrick Girard 001 (J. Low Power Electron., 2013)

Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation. - Aida Todri; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Arnaud Virazel (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A Study of Tapered 3-D TSVs for Power and Thermal Integrity. - Aida Todri; Sandip Kundu; Patrick Girard 001; Alberto Bosio; Luigi Dilillo; Arnaud Virazel (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration. - Yuanqing Cheng; Aida Todri-Sanial; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Arnaud Virazel (ASP-DAC, 2014)

On the Generation of Diagnostic Test Set for Intra-cell Defects. - Zhenzhou Sun; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Arnaud Virazel; Etienne Auvray (ATS, 2014)

Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. - Anu Asokan; Aida Todri-Sanial; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel (DDECS, 2014)

An intra-cell defect grading tool. - Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri-Sanial; Arnaud Virazel; S. Bernabovi; Paolo Bernardi (DDECS, 2014)

Timing-aware ATPG for critical paths with multiple TSVs. - Carolina Metzler; Aida Todri-Sanial; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Arnaud Virazel (DDECS, 2014)

Test and diagnosis of power switches. - Miroslav Valka; Alberto Bosio; Luigi Dilillo; Aida Todri; Arnaud Virazel; Patrick Girard 001; P. Debaud; S. Guilhot (DDECS, 2014)

Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults. - Imran Wali; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri (DDECS, 2014)

iBoX - Jitter based Power Supply Noise sensor. - Miroslav Valka; Alberto Bosio; Luigi Dilillo; Aida Todri; Arnaud Virazel; Patrick Girard 001; P. Debaud; S. Guilhot (ETS, 2014)

A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise. - Anu Asokan; Aida Todri-Sanial; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel (ISVLSI, 2014)

A Comprehensive Evaluation of Functional Programs for Power-Aware Test. - Aymen Touati; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri-Sanial; Arnaud Virazel; Paolo Bernardi (NATW, 2014)

TSV aware timing analysis and diagnosis in paths with multiple TSVs. - Carolina Metzler; Aida Todri-Sanial; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Arnaud Virazel (VTS, 2014)

Intra-Cell Defects Diagnosis. - Zhenzhou Sun; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Etienne Auvray (J. Electron. Test., 2014)

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. - D. A. Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Hans-Joachim Wunderlich (J. Electron. Test., 2014)

On the Test and Mitigation of Malfunctions in Low-Power SRAMs. - Leonardo Bonet Zordan; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Arnaud Virazel; Nabil Badereddine (J. Electron. Test., 2014)

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. - Akihiro Tomita; Xiaoqing Wen; Yasuo Sato; Seiji Kajihara; Kohei Miyase; Stefan Holst; Patrick Girard 001; Mohammad Tehranipoor; Laung-Terng Wang (IEICE Trans. Inf. Syst., 2014)

A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs. - Joao Azevedo; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri-Sanial; Jérémy Alvarez-Herault; Ken Mackay (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Globally Constrained Locally Optimized 3-D Power Delivery Networks. - Aida Todri-Sanial; Sandip Kundu; Patrick Girard 001; Alberto Bosio; Luigi Dilillo; Arnaud Virazel (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Exploring the impact of functional test programs re-used for power-aware testing. - Aymen Touati; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Arnaud Virazel; Paolo Bernardi; Matteo Sonza Reorda (DATE, 2015)

Design-for-Diagnosis Architecture for Power Switches. - Miroslav Valka; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Arnaud Virazel; P. Debaud; S. Guilhot (DDECS, 2015)

An effective ATPG flow for Gate Delay Faults. - Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Arnaud Virazel; Paolo Bernardi; Matteo Sonza Reorda (DTIS, 2015)

Scan-chain intra-cell defects grading. - Aymen Touati; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Arnaud Virazel; Paolo Bernardi; Matteo Sonza Reorda (DTIS, 2015)

An effective hybrid fault-tolerant architecture for pipelined cores. - Imran Wali; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001 (ETS, 2015)

An efficient hybrid power modeling approach for accurate gate-level power estimation. - Alejandro Nocua; Arnaud Virazel; Alberto Bosio; Patrick Girard 001; Cyril Chevalier (ICM, 2015)

Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture. - Imran Wali; Arnaud Virazel; Alberto Bosio; Patrick Girard 001; Matteo Sonza Reorda (IOLTS, 2015)

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. - Sylvain Clerc; Fady Abouzeid; Darayus Adil Patel; Jean-Marc Daveau; Cyril Bottoni; Lorenzo Ciampolini; Fabien Giner; David Meyer; Robin Wilson; Philippe Roche; Sylvie Naudet; Arnaud Virazel; et al. (ISQED, 2015)

An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern. - Anu Asokan; Alberto Bosio; Arnaud Virazel; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch (ISVLSI, 2015)

A hybrid power modeling approach to enhance high-level power models. - Alejandro Nocua; Arnaud Virazel; Alberto Bosio; Patrick Girard 001; Cyril Chevalier (DDECS, 2016)

An effective approach for functional test programs compaction. - Aymen Touati; Alberto Bosio; Patrick Girard 001; Arnaud Virazel; Paolo Bernardi; Matteo Sonza Reorda (DDECS, 2016)

Auto-adaptive ultra-low power IC. - Alberto Bosio; Philippe Debaud; Patrick Girard 001; Stephane Guilhot; Miroslav Valka; Arnaud Virazel (DTIS, 2016)

A low-cost susceptibility analysis methodology to selectively harden logic circuits. - Imran Wali; Bastien Deveautour; Arnaud Virazel; Alberto Bosio; Patrick Girard 001; Matteo Sonza Reorda (ETS, 2016)

Test of low power circuits: Issues and industrial practices. - Alberto Bosio; Patrick Girard 001; Arnaud Virazel (ICECS, 2016)

An effective BIST architecture for power-gating mechanisms in low-power SRAMs. - Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Arnaud Virazel; Leonardo Bonet Zordan (ISQED, 2016)

Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study. - Aymen Touati; Alberto Bosio; Patrick Girard 001; Arnaud Virazel; Paolo Bernardi; Matteo Sonza Reorda (ISVLSI, 2016)

A Hybrid Power Estimation Technique to improve IP power models quality. - Alejandro Nocua; Arnaud Virazel; Alberto Bosio; Patrick Girard 001; Cyril Chevalier (VLSI-SoC, 2016)

An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization. - Kapil Juneja; Darayus Adil Patel; Rajesh Kumar Immadi; Balwant Singh; Sylvie Naudet; Pankaj Agarwal; Arnaud Virazel; Patrick Girard 001 (J. Electron. Test., 2016)

A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores. - Imran Wali; Arnaud Virazel; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Matteo Sonza Reorda (J. Electron. Test., 2016)

Design for Test and Diagnosis of Power Switches. - Miroslav Valka; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Arnaud Virazel; Philippe Debaud; Stephane Guilhot (J. Circuits Syst. Comput., 2016)

Towards approximation during test of Integrated Circuits. - Imran Wali; Marcello Traiola; Arnaud Virazel; Patrick Girard 001; Mario Barbareschi; Alberto Bosio (DDECS, 2017)

An effective fault-injection framework for memory reliability enhancement perspectives. - G. Harcha; Alberto Bosio; Patrick Girard 001; Arnaud Virazel; Paolo Bernardi (DTIS, 2017)

Towards digital circuit approximation by exploiting fault simulation. - Marcello Traiola; Arnaud Virazel; Patrick Girard 001; Mario Barbareschi; Alberto Bosio (EWDTS, 2017)

Approximate computing: Design & test for integrated circuits. - Alberto Bosio; Arnaud Virazel; Patrick Girard 001; Mario Barbareschi (LATS, 2017)

A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits. - Imran Wali; Bastien Deveautour; Arnaud Virazel; Alberto Bosio; Patrick Girard 001; Matteo Sonza Reorda (J. Electron. Test., 2017)

HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization. - Alejandro Nocua; Arnaud Virazel; Alberto Bosio; Patrick Girard 001; Cyril Chevalier (J. Circuits Syst. Comput., 2017)

Microprocessor Testing: Functional Meets Structural Test. - Aymen Touati; Alberto Bosio; Patrick Girard 001; Arnaud Virazel; Paolo Bernardi; Matteo Sonza Reorda (J. Circuits Syst. Comput., 2017)

A Special Section on New and Future Trends in Low Power Electronics. - Patrick Girard 001 (J. Low Power Electron., 2017)

A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality. - Alejandro Nocua; Arnaud Virazel; Alberto Bosio; Patrick Girard 001; Cyril Chevalier (J. Low Power Electron., 2017)

On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits. - Marcello Traiola; Arnaud Virazel; Patrick Girard 001; Mario Barbareschi; Alberto Bosio (DDECS, 2018)

Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits. - Marcello Traiola; Arnaud Virazel; Patrick Girard 001; Mario Barbareschi; Alberto Bosio (DFT, 2018)

Is aproximate computing suitable for selective hardening of arithmetic circuits? - Bastien Deveautour; Arnaud Virazel; Patrick Girard 001; Serge Pravossoudovitch; Valentin Gherman (DTIS, 2018)

Power-aware testing in the Era of IoT. - Patrick Girard 001 (ISQED, 2018)

An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs. - Tien-Phu Ho; Eric Faehn; Arnaud Virazel; Alberto Bosio; Patrick Girard 001 (ITC, 2018)

Testing approximate digital circuits: Challenges and opportunities. - Marcello Traiola; Arnaud Virazel; Patrick Girard 001; Mario Barbareschi; Alberto Bosio (LATS, 2018)

A Special Section on Low Power Electronics: A Compilation of Emerging Ideas and Efficient Solutions. - Patrick Girard 001 (J. Low Power Electron., 2018)

A Special Section on Industrial Experiences in Low Power Electronics. - Patrick Girard 001 (J. Low Power Electron., 2018)

A Special Section On Machine Learning and Artificial Intelligence In Low Power Electronics. - Patrick Girard 001 (J. Low Power Electron., 2018)

Scan-Chain Intra-Cell Aware Testing. - Aymen Touati; Alberto Bosio; Patrick Girard 001; Arnaud Virazel; Paolo Bernardi; Matteo Sonza Reorda; Etienne Auvray (IEEE Trans. Emerg. Top. Comput., 2018)

Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications. - Aibin Yan; Zhen Wu; Lu Lu; Zhili Chen; Jie Song; Zuobin Ying; Patrick Girard 001; Xiaoqing Wen (ATS, 2019)

Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications. - Aibin Yan; Zhen Wu; Jun Zhou 016; Yuanjie Hu; Yan Chen; Zuobin Ying; Xiaoqing Wen; Patrick Girard 001 (ATS, 2019)

Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip. - Safa Mhamdi; Arnaud Virazel; Patrick Girard 001; Alberto Bosio; Etienne Auvray; Eric Faehn; Aymen Ladhar (IOLTS, 2019)

A Capacitor-Less CMOS Neuron Circuit for Neuromemristive Networks. - Hassen Aziza; Mathieu Moreau; Annie Pérez; Arnaud Virazel; Patrick Girard 001 (NEWCAS, 2019)

Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets. - Aibin Yan; Jun Zhou 016; Yuanjie Hu; Jie Cui 004; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (IEEE Access, 2019)

A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets. - Aibin Yan; Yan Chen; Jun Zhou 016; Jie Cui 004; Tianming Ni; Xiaoqing Wen; Patrick Girard 001 (ATS, 2020)

HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications. - Aibin Yan; Xiangfeng Feng; Xiaohu Zhao; Hang Zhou; Jie Cui 004; Zuobin Ying; Patrick Girard 001; Xiaoqing Wen (DAC, 2020)

Maximizing Yield for Approximate Integrated Circuits. - Marcello Traiola; Arnaud Virazel; Patrick Girard 001; Mario Barbareschi; Alberto Bosio (DATE, 2020)

Design, Verification, Test and In-Field Implications of Approximate Computing Systems. - Alberto Bosio; Stefano Di Carlo; Patrick Girard 001; Ernesto Sánchez 001; Alessandro Savino; Lukás Sekanina; Marcello Traiola; Zdenek Vasícek; Arnaud Virazel (ETS, 2020)

QAMR: an Approximation-Based Fully Reliable TMR Alternative for Area Overhead Reduction. - Bastien Deveautour; Marcello Traiola; Arnaud Virazel; Patrick Girard 001 (ETS, 2020)

Learning-Based Cell-Aware Defect Diagnosis of Customer Returns. - Safa Mhamdi; Patrick Girard 001; Arnaud Virazel; Alberto Bosio; Aymen Ladhar (ETS, 2020)

Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs. - Florence Azaïs; Serge Bernard; Mariane Comte; Bastien Deveautour; Sophie Dupuis; Hassan El Badawi; Marie-Lise Flottes; Patrick Girard 001; Vincent Kerzèrho; Laurent Latorre; François Lefèvre; Bruno Rouzeyre; et al. (IOLTS, 2020)

An ECC-Based Repair Approach with an Offset-Repair CAM for Mitigating the MBUs Affecting Repair CAM. - Panagiota Papavramidou; Michael Nicolaidis; Patrick Girard 001 (IOLTS, 2020)

Impact of Aging on Soft Error Susceptibility in CMOS Circuits. - Ambika Prasad Shah; Patrick Girard 001 (IOLTS, 2020)

A CMOS OxRAM-Based Neuron Circuit Hardened with Enclosed Layout Transistors for Aerospace Applications. - Pablo Ilha Vaz; Patrick Girard 001; Arnaud Virazel; Hassen Aziza (IOLTS, 2020)

Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications. - Aibin Yan; Zhelong Xu; Jie Cui 004; Zuobin Ying; Zhengfeng Huang; Huaguo Liang; Patrick Girard 001; Xiaoqing Wen (ISCAS, 2020)

DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache. - Jinbo Chen; Keren Liu; Xiaochen Guo; Patrick Girard 001; Yuanqing Cheng (ISQED, 2020)

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors. - Zhengda Dou; Aibin Yan; Jun Zhou 016; Yuanjie Hu; Yan Chen; Tianming Ni; Jie Cui 004; Patrick Girard 001; Xiaoqing Wen (ITC-Asia, 2020)

A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns. - Safa Mhamdi; Patrick Girard 001; Arnaud Virazel; Alberto Bosio; Aymen Ladhar (ITC, 2020)

On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits. - Bastien Deveautour; Arnaud Virazel; Patrick Girard 001; Valentin Gherman (J. Electron. Test., 2020)

A Survey of Testing Techniques for Approximate Integrated Circuits. - Marcello Traiola; Arnaud Virazel; Patrick Girard 001; Mario Barbareschi; Alberto Bosio (Proc. IEEE, 2020)

Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low-Power and Low-Orbit Aerospace Applications. - Aibin Yan; Yan Chen; Zhelong Xu; Zhili Chen; Jie Cui 004; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Aerosp. Electron. Syst., 2020)

A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications. - Aibin Yan; Zhelong Xu; Kang Yang; Jie Cui 004; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Aerosp. Electron. Syst., 2020)

Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment. - Aibin Yan; Yuanjie Hu; Jie Cui 004; Zhili Chen; Zhengfeng Huang; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Computers, 2020)

Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets. - Aibin Yan; Yan Chen; Yuanjie Hu; Jun Zhou 016; Tianming Ni; Jie Cui 004; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Circuits Syst., 2020)

Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs. - Aibin Yan; Yafei Ling; Jie Cui 004; Zhili Chen; Zhengfeng Huang; Jie Song; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A Learning-Based Methodology for Accelerating Cell-Aware Model Generation. - P. D'Hondt; Aymen Ladhar; Patrick Girard 001; Arnaud Virazel (DATE, 2021)

Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures. - Lila Ammoura; Marie-Lise Flottes; Patrick Girard 001; Arnaud Virazel (DTIS, 2021)

Emerging Computing Devices: Challenges and Opportunities for Test and Reliability*. - Alberto Bosio; Ian O'Connor; Marcello Traiola; Jorge Echavarria; Jürgen Teich; Muhammad Abdullah Hanif; Muhammad Shafique 001; Said Hamdioui; Bastien Deveautour; Patrick Girard 001; Arnaud Virazel; Koen Bertels (ETS, 2021)

Design of Fault-Tolerant and Thermally Stable XOR Gate in Quantum dot Cellular Automata. - Syed Farah Naz; Ambika Prasad Shah; Suhaib Ahmed; Patrick Girard 001; Michael Waltl (ETS, 2021)

Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits. - Neha Gupta; Nikhil Agrawal; Narendra Singh Dhakad; Ambika Prasad Shah; Santosh Kumar Vishvakarma; Patrick Girard 001 (ACM Great Lakes Symposium on VLSI, 2021)

A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments. - Aibin Yan; Aoran Cao; Zhengzheng Fan; Zhelong Xu; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (ACM Great Lakes Symposium on VLSI, 2021)

Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement. - Riccardo Cantoro; Patrick Girard 001; Riccardo Masante; Sandro Sartoni; Matteo Sonza Reorda; Arnaud Virazel (IOLTS, 2021)

Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate Computing. - Bastien Deveautour; Marcello Traiola; Arnaud Virazel; Patrick Girard 001 (IOLTS, 2021)

Cell-Aware Diagnosis of Customer Returns Using Bayesian Inference. - Safa Mhamdi; Patrick Girard 001; Arnaud Virazel; Alberto Bosio; Aymen Ladhar (ISQED, 2021)

A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors. - Julia Lefevre; Philippe Debaud; Patrick Girard 001; Arnaud Virazel (ITC, 2021)

Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications. - Aibin Yan; Aoran Cao; Zhelong Xu; Jie Cui 004; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (J. Electron. Test., 2021)

Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications. - Aibin Yan; Zhihui He; Jun Zhou 016; Jie Cui 004; Tianming Ni; Zhengfeng Huang; Xiaoqing Wen; Patrick Girard 001 (Microelectron. J., 2021)

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories. - Patrick Girard 001; Yuanqing Cheng; Arnaud Virazel; Wei Zhao 010; Rajendra Bishnoi; Mehdi B. Tahoori (Proc. IEEE, 2021)

DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect. - Jinbo Chen; Chengcheng Lu; Jiacheng Ni; Xiaochen Guo; Patrick Girard 001; Yuanqing Cheng (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors. - Pablo Ilha Vaz; Patrick Girard 001; Arnaud Virazel; Hassen Aziza (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Test and Reliability of Approximate Hardware. - Marcello Traiola; Bastien Deveautour; Alberto Bosio; Patrick Girard 001; Arnaud Virazel (Approximate Computing, 2022)

A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage. - Aibin Yan; Liang Ding; Zhen Zhou; Zhengfeng Huang; Jie Cui 004; Patrick Girard 001; Xiaoqing Wen (ATS, 2022)

SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments. - Aibin Yan; Zhixing Li; Shiwei Huang; Zijie Zhai; Xiangyu Cheng; Jie Cui 004; Tianming Ni; Xiaoqing Wen; Patrick Girard 001 (DATE, 2022)

Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries. - Riccardo Cantoro; Francesco Garau; Patrick Girard 001; Nima Kolahimahmoudi; Sandro Sartoni; Matteo Sonza Reorda; Arnaud Virazel (ETS, 2022)

A Generic Fast and Low Cost BIST Solution for CMOS Image Sensors. - Julia Lefevre; P. Debaud; Patrick Girard 001; Arnaud Virazel (ETS, 2022)

Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications. - Aibin Yan; Yu Chen; Shukai Song; Zijie Zhai; Jie Cui 004; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (ACM Great Lakes Symposium on VLSI, 2022)

Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications. - Aibin Yan; Zhihui He; Jing Xiang; Jie Cui 004; Yong Zhou; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (ACM Great Lakes Symposium on VLSI, 2022)

A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology. - Aibin Yan; Zhen Zhou; Shaojie Wei; Jie Cui 004; Yong Zhou; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (ACM Great Lakes Symposium on VLSI, 2022)

Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS. - Aibin Yan; Shukai Song; Jixiang Zhang 007; Jie Cui 004; Zhengfeng Huang; Tianming Ni; Xiaoqing Wen; Patrick Girard 001 (ITC-Asia, 2022)

A Comprehensive Learning-Based Flow for Cell-Aware Model Generation. - P. D'Hondt; Aymen Ladhar; Patrick Girard 001; Arnaud Virazel (ITC, 2022)

A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications. - Aibin Yan; Kuikui Qian; Jie Cui 004; Ningning Cui; Zhengfeng Huang; Xiaoqing Wen; Patrick Girard 001 (VTS, 2022)

All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits. - Kangwei Xu; Dongrong Zhang; Qiang Ren; Yuanqing Cheng; Patrick Girard 001 (ACM J. Emerg. Technol. Comput. Syst., 2022)

Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications. - Aibin Yan; Zhengzheng Fan; Liang Ding; Jie Cui 004; Zhengfeng Huang; Qijun Wang; Hao Zheng; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Aerosp. Electron. Syst., 2022)

Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments. - Aibin Yan; Zhelong Xu; Xiangfeng Feng; Jie Cui 004; Zhili Chen; Tianming Ni; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Emerg. Top. Comput., 2022)

High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology. - Aibin Yan; Zhen Zhou; Liang Ding; Jie Cui 004; Zhengfeng Huang; Xiaoqing Wen; Patrick Girard 001 (DATE, 2023)

Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC Architecture. - Lila Ammoura; Marie-Lise Flottes; Patrick Girard 001; Jean-Philippe Noel; Arnaud Virazel (ETS, 2023)

Learning-Based Characterization Models for Quality Assurance of Emerging Memory Technologies. - Xhesila Xhafa; Patrick Girard 001; Arnaud Virazel (ETS, 2023)

On Using Cell-Aware Methodology for SRAM Bit Cell Testing. - Xhesila Xhafa; Aymen Ladhar; Eric Faehn; Lorena Anghel; Gregory di Pendina; Patrick Girard 001; Arnaud Virazel (ETS, 2023)

A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications. - Aibin Yan; Shaojie Wei; Jinjun Zhang; Jie Cui 004; Jie Song; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (ACM Great Lakes Symposium on VLSI, 2023)

Design of Low-Cost Approximate CMOS Full Adders. - Aibin Yan; Shaojie Wei; Zhixing Li; Jie Cui 004; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (ISCAS, 2023)

Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications. - Aibin Yan; Jing Xiang; Zhengfeng Huang; Tianming Ni; Jie Cui 004; Patrick Girard 001; Xiaoqing Wen (ITC-Asia, 2023)

A Low Overhead and Double-Node-Upset Self-Recoverable Latch. - Aibin Yan; Fan Xia; Tianming Ni; Jie Cui 004; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (ITC-Asia, 2023)

Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness. - Aibin Yan; Chao Zhou; Shaojie Wei; Jie Cui 004; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (ITC-Asia, 2023)

Predictor BIST: An "All-in-One" Optical Test Solution for CMOS Image Sensors. - Julia Lefevre; P. Debaud; Patrick Girard 001; Arnaud Virazel (ITC, 2023)

Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications. - Aibin Yan; Aoran Cao; Zhengfeng Huang; Jie Cui 004; Tianming Ni; Patrick Girard 001; Xiaoqing Wen; Jiliang Zhang 002 (IEEE Trans. Emerg. Top. Comput., 2023)

Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments. - Aibin Yan; Zhixing Li; Jie Cui 004; Zhengfeng Huang; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Aerosp. Electron. Syst., 2023)

LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments. - Aibin Yan; Zhixing Li; Jie Cui 004; Zhengfeng Huang; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata. - Aibin Yan; Runqi Liu; Jie Cui 004; Tianming Ni; Patrick Girard 001; Xiaoqing Wen; Jiliang Zhang 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications. - Aibin Yan; Yuting He; Xiaoxiao Niu; Jie Cui 004; Tianming Ni; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (IEEE Des. Test, 2023)

Two sextuple cross-coupled SRAM cells with double-node-upset protection and cost optimization for aerospace applications. - Aibin Yan; Jing Xiang; Yang Chang; Zhengfeng Huang; Jie Cui 004; Patrick Girard 001; Xiaoqing Wen (Microelectron. J., 2023)

A Novel March Test Algorithm for Testing 8T SRAM-Based IMC Architectures. - Lila Ammoura; Marie-Lise Flottes; Patrick Girard 001; Jean-Philippe Noel; Arnaud Virazel (DATE, 2024)

A Structural Testing Approach for SRAM Address Decoders Using Cell-Aware Methodology. - Xhesila Xhafa; Eric Faehn; Patrick Girard 001; Arnaud Virazel (DFT, 2024)

Producing a Bidirectional ATPG Compliant Verilog-HDL Memory Model of SRAM. - D. Ronga; Xhesila Xhafa; Eric Faehn; Patrick Girard 001; Thibault Vayssade; Arnaud Virazel (DTTIS, 2024)

IDLD: Interlocked Dual-Circle Latch Design with Low Cost and Triple-Node-Upset-Recovery for Aerospace Applications. - Aibin Yan; Chen Dong; Xing Guo; Jie Song; Jie Cui 004; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (ACM Great Lakes Symposium on VLSI, 2024)

A Graph-Based Methodology for Speeding up Cell-Aware Model Generation. - Gianmarco Mongelli; Xhesila Xhafa; Eric Faehn; Dylan Robins; Patrick Girard 001; Arnaud Virazel (IOLTS, 2024)

Nonvolatile and SEU-Recoverable Latch Based on FeFET and CMOS for Energy-Harvesting Devices. - Aibin Yan; Zhuoyuan Lin; Guangzhu Liu; Qingyang Zhang; Zhengfeng Huang; Jie Cui 004; Xiaoqing Wen; Patrick Girard 001 (ISCAS, 2024)

A Fast and Efficient Graph-Based Methodology for Cell-Aware Model Generation. - Gianmarco Mongelli; Eric Faehn; Dylan Robins; Patrick Girard 001; Arnaud Virazel (ITC, 2024)

Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS. - Aibin Yan; Litao Wang; Jie Cui 004; Zhengfeng Huang; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Very Large Scale Integr. Syst., 2024)

FeMPIM: A FeFET-Based Multifunctional Processing-in-Memory Cell. - Aibin Yan; Yu Chen; Zhongyu Gao; Tianming Ni; Zhengfeng Huang; Jie Cui 004; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method. - Aibin Yan; Zhixing Li; Zhongyu Gao; Jing Zhang; Zhengfeng Huang; Tianming Ni; Jie Cui 004; Xiaolei Wang; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Accelerating Cell-Aware Model Generation for Sequential Cells using Graph Theory. - Gianmarco Mongelli; Eric Faehn; Dylan Robins; Patrick Girard 001; Arnaud Virazel (DATE, 2025)

NVSRLO: A FeFET-Based Non-Volatile and SEU-Recoverable Latch Design with Optimized Overhead. - Aibin Yan; Wangjin Jiang; Han Bao; Zhengfeng Huang; Tianming Ni; Xiaoqing Wen; Patrick Girard 001 (DATE, 2025)

A Runtime Efficient Graph-Based Cell-Aware Model Generation for Structural SRAM Testing. - Gianmarco Mongelli; Xhesila Xhafa; Eric Faehn; Dylan Robins; Patrick Girard 001; Arnaud Virazel (IOLTS, 2025)

A Digital SRAM Modeling for Cell-Aware Testing and Test Algorithms Evaluation. - D. Ronga; Xhesila Xhafa; Eric Faehn; Patrick Girard 001; T. Vayssade; Arnaud Virazel (IOLTS, 2025)

TNURML: Triple-Node-Upset-Recovery Magnetic Latch Design with Non-Volatility for Aerospace Applications. - Aibin Yan; Zhiyuan Pei; Xing Guo; Jie Song; Cuiyun Jiang; Huaguo Liang; Xiaoqing Wen; Patrick Girard 001 (ISCAS, 2025)

Cost Efficient Flip-Flop Designs With Multiple-Node Upset-Tolerance and Algorithm-Based Verifications. - Aibin Yan; Yuting He; Zhengfeng Huang; Wenjie Yan; Jie Cui 004; Xiaolei Wang; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

SRAM Periphery Testing Using the Cell-Aware Test Methodology. - Xhesila Xhafa; Eric Faehn; Patrick Girard 001; Arnaud Virazel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Graph-Based Multitask Transfer Learning for Fault Detection and Diagnosis of Few-Shot Analog Circuits. - Zhongyu Gao; Aibin Yan; Zhengfeng Huang; Jie Cui 004; Byeong-Hee Roh; Guangzhu Liu; Patrick Girard 001; Xiaoqing Wen (IEEE Internet Things J., 2025)

Cost-Optimized and Highly Robust Latches Providing Complete Quadruple-Node-Upset Tolerance and Recovery With Algorithm-Based Verifications. - Aibin Yan; Chao Zhou; Tianming Ni; Jing Zhang; Jie Cui 004; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Aerosp. Electron. Syst., 2025)

HALTRAV: Design of a High-Performance and Area-Efficient Latch With Triple-Node-Upset Recovery and Algorithm-Based Verifications. - Xing Guo; Jiajia Zhang; Xu Meng; Zhenmin Li; Xiaoqing Wen; Patrick Girard 001; Bin Liang; Aibin Yan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Cost-Optimized Double-Node-Upset-Recovery Latch Designs With Aging Mitigation and Algorithm-Based Verification for Long-Term Robustness Enhancement. - Aibin Yan; Changli Hu; Jing Li; Na Bai; Zhengfeng Huang; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Design of Nonvolatile and Multinode-Upset Recoverable Latches Based on Magnetic Tunnel Junction and CMOS. - Aibin Yan; Yongkang Xu; Yue Zhang; Na Bai; Zhengfeng Huang; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Triple-Node-Upset Recovery High-Impedance-State-Insensitive and Single-Event-Transient Filtering Latch for Aerospace Applications. - Aibin Yan; Zhuoyuan Lin; Yongkang Xu; Na Bai; Jie Cui 004; Zhengfeng Huang; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Aerosp. Electron. Syst., 2025)