The S/390 G5/G6 binodal cache. - Paul R. Turgeon; Pak-kin Mak; Michael A. Blake; Michael F. Fee; Carl B. Ford III; Patrick J. Meaney; A. E. (Rick) Seigler; William Wu Shen (IBM J. Res. Dev., 1999)

RAS design for the IBM eServer z900. - Luiz C. Alves; Myron L. Fair; Patrick J. Meaney; C. L. Chen; William J. Clarke; George C. Wellwood; Norman E. Weber; Indravadan N. Modi; Brian K. Tolan; Fritz Freier (IBM J. Res. Dev., 2002)

Reliability, availability, and serviceability (RAS) of the IBM eServer z990. - Myron L. Fair; Christopher R. Conklin; Scott B. Swaney; Patrick J. Meaney; William J. Clarke; Luiz C. Alves; Indravadan N. Modi; Fritz Freier; Wolfgang Fischer 001; Norman E. Weber (IBM J. Res. Dev., 2004)

A 5.2GHz microprocessor chip for the IBM zEnterprise™ system. - James D. Warnock; Y. Chan; William V. Huott; Sean M. Carey; Michael F. Fee; Huajun Wen; Mary Jo Saccamango; Frank Malgioglio; Patrick J. Meaney; Donald W. Plass; Yuen H. Chan; Mark D. Mayo; et al. (ISSCC, 2011)

A new class of array codes for memory storage. - Luis Alfonso Lastras-Montaño; Patrick J. Meaney; Eldee Stephens; Barry M. Trager; James A. O'Connor; Luiz C. Alves (ITA, 2011)

The zEnterprise 196 System and Microprocessor. - Brian W. Curran; Lee Eisen; Eric M. Schwarz; Pak-kin Mak; James D. Warnock; Patrick J. Meaney; Michael F. Fee (IEEE Micro, 2011)

IBM zEnterprise redundant array of independent memory subsystem. - Patrick J. Meaney; Luis Alfonso Lastras-Montaño; Vesselina K. Papazova; Eldee Stephens; J. S. Johnson; Luiz C. Alves; James A. O'Connor; William J. Clarke (IBM J. Res. Dev., 2012)

Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System. - James D. Warnock; Yiu-Hing Chan; Sean M. Carey; Huajun Wen; Patrick J. Meaney; Guenter Gerwig; Howard H. Smith; Yuen H. Chan; John Davis; Paul Bunce; Antonio Pelella; Daniel Rodko; et al. (IEEE J. Solid State Circuits, 2012)

The IBM z13 memory subsystem for big data. - Patrick J. Meaney; L. D. Curley; G. D. Gilda; M. R. Hodges; D. J. Buerkle; R. D. Siegl; R. K. Dong (IBM J. Res. Dev., 2015)

Synchronous, Low-Latency, Off-Module Interface for the IBM z16 Telum Processor. - Patrick J. Meaney; Ashutosh Mishra; Rajat Rao (IEEE Micro, 2024)

2.2 IBM Telum II: Next Generation 5.5GHz Microprocessor with On-Die Data Processing Unit and Improved AI Accelerator. - Gerald Strevig; Christopher J. Berry; Rahul M. Rao; Noam Jungmann; Michael A. Sperling; Michael J. Becht; Eduard Herkel; Matthias Pflanz; Patrick J. Meaney; Michael Romain; Mark Cichanowski; Amanda Venton; et al. (ISSCC, 2025)