Die Stacking (3D) Microarchitecture. - Bryan Black; Murali Annavaram; Ned Brekelbaum; John DeVale; Lei Jiang; Gabriel H. Loh; Don McCaule; Patrick Morrow; Donald W. Nelson; Daniel Pantuso; Paul Reed; Jeff Rupley; et al. (MICRO, 2006)

Ultra high density logic designs using transistor-level monolithic 3D integration. - Young-Joon Lee; Patrick Morrow; Sung Kyu Lim (ICCAD, 2012)

How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core. - Moongon Jung; Taigon Song; Yang Wan; Young-Joon Lee; Debabrata Mohapatra; Hong Wang; Greg Taylor; Devang Jariwala; Vijay Pitchumani; Patrick Morrow; Clair Webb; Paul Fischer; et al. (CICC, 2013)

Novel Cell Architectures with Back-side Transistor Contacts for Scaling and Performance. - Mauro J. Kobrinsky; J. D. Silva; E. Mannebach; S. Mills; M. Abd El Qader; O. Adebayo; N. Arkali Radhakrishna; M. Beasley; J. Chawla; S. Chugh; A. Dasgupta; U. Desai; et al. (VLSI Technology and Circuits, 2023)