The Evolution of IT Security Convergence. - Patrick R. Gallagher Jr. (SEC, 1993)

A building block BIST methodology for SOC designs: a case study. - Patrick R. Gallagher Jr.; Vivek Chickermane; Steven Gregor; Thomas S. Pierre (ITC, 2001)

Test Generation for State Retention Logic. - Krishna Chakravadhanula; Vivek Chickermane; Brion L. Keller; Patrick R. Gallagher Jr.; Steven Gregor (ATS, 2008)

A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs. - Vivek Chickermane; Patrick R. Gallagher Jr.; James Sage; Paul Yuan; Krishna Chakravadhanula (ITC, 2008)

Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?. - Krishna Chakravadhanula; Vivek Chickermane; Brion L. Keller; Patrick R. Gallagher Jr.; Anis Uzzaman (Asian Test Symposium, 2009)

Capture power reduction using clock gating aware test generation. - Krishna Chakravadhanula; Vivek Chickermane; Brion L. Keller; Patrick R. Gallagher Jr.; Prashant Narang (ITC, 2009)