Bandwidth Mismatch Correction for a Two-Channel Time-Interleaved A/D Converter. - Patrick Satarzadeh; Bernard C. Levy; Paul J. Hurst (ISCAS, 2007)

Digital Calibration of a Nonlinear S/H. - Patrick Satarzadeh; Bernard C. Levy; Paul J. Hurst (IEEE J. Sel. Top. Signal Process., 2009)

Adaptive Semiblind Calibration of Bandwidth Mismatch for Two-Channel Time-Interleaved ADCs. - Patrick Satarzadeh; Bernard C. Levy; Paul J. Hurst (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Equalizer design and performance trade-offs in ADC-based serial links. - Jaeha Kim; Jihong Ren; Brian S. Leibowitz; Patrick Satarzadeh; Ali-Azam Abbasfar; Jared Zerbe (CICC, 2010)

A parametric polyphase domain approach to blind calibration of timing mismatches for M-channel time-interleaved ADCs. - Patrick Satarzadeh; Bernard C. Levy; Paul J. Hurst (ISCAS, 2010)

A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques. - Jared Zerbe; Barry Daly; Lei Luo 006; Bill Stonecypher; Wayne D. Dettloff; John C. Eble; Teva Stone; Jihong Ren; Brian S. Leibowitz; Michael Bucher; Patrick Satarzadeh; Qi Lin; et al. (IEEE J. Solid State Circuits, 2011)

Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links. - Jaeha Kim; E-Hung Chen; Jihong Ren; Brian S. Leibowitz; Patrick Satarzadeh; Jared Zerbe; Chih-Kong Ken Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A 20mW 61dB SNDR (60MHz BW) 1b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS. - Venkatesh Srinivasan; Victoria Wang; Patrick Satarzadeh; Baher Haroun; Marco Corsi (ISSCC, 2012)

Digital Correction of Time Interleaved DAC Mismatches. - Garen Hovakimyan; Pirooz Hojabri; Gregory A. Martin; Patrick Satarzadeh (ISCAS, 2019)