Model-based hardware design based on compatible sets of isomorphic subgraphs. - Patrick Sittel; Konrad Möller; Martin Kumm; Peter Zipf; Bogdan Pasca 001; Mark Jervis (FPT, 2017)

High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits. - Patrick Sittel; Martin Kumm; Konrad Möller; Martin Hardieck; Peter Zipf (MBMV, 2017)

ILP-Based Modulo Scheduling and Binding for Register Minimization. - Patrick Sittel; Martin Kumm; Julian Oppermann; Konrad Möller; Peter Zipf; Andreas Koch 001 (FPL, 2018)

Constant Matrix Multiplication with Ternary Adders. - Martin Hardieck; Martin Kumm; Patrick Sittel; Peter Zipf (ICECS, 2018)

ScaLP: A Light-Weighted (MI)LP-Library. - Patrick Sittel; Thomas Schönwälder; Martin Kumm; Peter Zipf (MBMV, 2018)

Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling. - Julian Oppermann; Patrick Sittel; Martin Kumm; Melanie Reuter-Oppermann; Andreas Koch 001; Oliver Sinnen (Euro-Par, 2019)

Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling. - Patrick Sittel; Nicolai Fiege; Martin Kumm; Peter Zipf (ReConFig, 2019)

Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design. - Patrick Sittel; John Wickerson; Martin Kumm; Peter Zipf (ASP-DAC, 2020)

Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling. - Nicolai Fiege; Patrick Sittel; Peter Zipf (FCCM, 2022)

Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis. - Nicolai Fiege; Patrick Sittel; Peter Zipf (FPL, 2022)

Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals. - Nicolai Fiege; Patrick Sittel; Peter Zipf (FPL, 2022)

Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis. - Patrick Sittel; Nicolai Fiege; John Wickerson; Peter Zipf (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)