A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. - Pei-Wen Luo; Chi-Kang Chen; Yu-Hui Sung; Wei Wu 024; Hsiu-Chuan Shih; Chia-Hsin Lee; Kuo-Hua Lee; Ming-Wei Li; Mei-Chiang Lung; Chun-Nan Lu; Yung-Fa Chou; Po-Lin Shih; et al. (VLSIC, 2015)

23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache. - Tah-Kang Joseph Ting; Gyh-Bin Wang; Ming-Hung Wang; Chun-Peng Wu; Chun-Kai Wang; Chun-Wei Lo; Li-Chin Tien; Der-Min Yuan; Yung-Ching Hsieh; Jenn-Shiang Lai; Wen-Pin Hsu; Chien-Chih Huang; et al. (ISSCC, 2017)

Probabilistic replacement strategies for improving the lifetimes of NVM-based caches. - Elizabeth Reed; Alaa R. Alameldeen; Helia Naeimi; Patrick Stolt (MEMSYS, 2017)