Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification. - Luca Benini; Patrick Vuillod; Claudionor José Nunes Coelho Jr.; Giovanni De Micheli (ISSS, 1996)

Generalized matching from theory to application. - Patrick Vuillod; Luca Benini; Giovanni De Micheli (ICCAD, 1997)

Re-mapping for low power under tight timing constraints. - Patrick Vuillod; Luca Benini; Giovanni De Micheli (ISLPED, 1997)

Clock Skew Optimization for Peak Current Reduction. - Luca Benini; Patrick Vuillod; Alessandro Bogliolo; Giovanni De Micheli (J. VLSI Signal Process., 1997)

Iterative remapping for logic circuits. - Luca Benini; Patrick Vuillod; Giovanni De Micheli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Multi-level logic benchmarks: An exactness study. - Luca Gaetano Amarù; Mathias Soeken; Winston Haaswijk; Eleonora Testa; Patrick Vuillod; Jiong Luo; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ASP-DAC, 2017)

Logic optimization and synthesis: Trends and directions in industry. - Luca Gaetano Amarù; Patrick Vuillod; Jiong Luo; Janet Olson (DATE, 2017)

Enabling exact delay synthesis. - Luca Gaetano Amarù; Mathias Soeken; Patrick Vuillod; Jiong Luo; Alan Mishchenko; Pierre-Emmanuel Gaillardon; Janet Olson; Robert K. Brayton; Giovanni De Micheli (ICCAD, 2017)

Improvements to boolean resynthesis. - Luca Gaetano Amarù; Mathias Soeken; Patrick Vuillod; Jiong Luo; Alan Mishchenko; Janet Olson; Robert K. Brayton; Giovanni De Micheli (DATE, 2018)

Integrated ESOP Refactoring for Industrial Designs. - Winston Haaswijk; Luca Gaetano Amarù; Patrick Vuillod; Jiong Luo; Mathias Soeken; Giovanni De Micheli (ICECS, 2018)

Scalable Boolean Methods in a Modern Synthesis Flow. - Eleonora Testa; Luca G. Amarù; Mathias Soeken; Alan Mishchenko; Patrick Vuillod; Jiong Luo; Christopher Casares; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (DATE, 2019)

SAT-Sweeping Enhanced for Logic Synthesis. - Luca G. Amarù; Felipe S. Marranghello; Eleonora Testa; Christopher Casares; Vinicius N. Possani; Jiong Luo; Patrick Vuillod; Alan Mishchenko; Giovanni De Micheli (DAC, 2020)

Extending Boolean Methods for Scalable Logic Synthesis. - Eleonora Testa; Luca G. Amarù; Mathias Soeken; Alan Mishchenko; Patrick Vuillod; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (IEEE Access, 2020)

LUT-Based Optimization For ASIC Design Flow. - Luca Gaetano Amarù; Vinicius N. Possani; Eleonora Testa; Felipe S. Marranghello; Christopher Casares; Jiong Luo; Patrick Vuillod; Alan Mishchenko; Giovanni De Micheli (DAC, 2021)

Improving LUT-based optimization for ASICs. - Walter Lau Neto; Luca G. Amarù; Vinicius Possani; Patrick Vuillod; Jiong Luo; Alan Mishchenko; Pierre-Emmanuel Gaillardon (DAC, 2022)

Majority-based Design Flow for AQFP Superconducting Family. - Giulia Meuli; Vinicius N. Possani; Rajinder Singh; Siang-Yun Lee; Alessandro Tempia Calvino; Dewmini Sudara Marakkalage; Patrick Vuillod; Luca G. Amarù; Scott Chase; Jamil Kawa; Giovanni De Micheli (DATE, 2022)