Directory and Trace memory chip with active discharge cell. - Paul Bunce; William Chin; Leo Clark; Barry Krumm (IBM J. Res. Dev., 1992)

Design validation of .18 μm 1 GHz cache and register arrays. - Doug Malone; Paul Bunce; Joe DellaPietro; John Davis; James Dawson; Thomas J. Knips; Don Plass; Phil Pritzlaff; Kenneth Reyer (CICC, 2000)

A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor. - John Davis; Don Plass; Paul Bunce; Yuen H. Chan; Antonio Pelella; Rajiv V. Joshi; A. Chen; William V. Huott; Thomas J. Knips; Pradip Patel; K. Lo; Eric Fluhr (ISSCC, 2006)

Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System. - James D. Warnock; Yiu-Hing Chan; Sean M. Carey; Huajun Wen; Patrick J. Meaney; Guenter Gerwig; Howard H. Smith; Yuen H. Chan; John Davis; Paul Bunce; Antonio Pelella; Daniel Rodko; et al. (IEEE J. Solid State Circuits, 2012)

7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor. - John Davis; Paul Bunce; Diana M. Henderson; Yuen H. Chan; Uma Srinivasan 002; Daniel Rodko; Pradip Patel; Thomas J. Knips; Tobias Werner 001 (ISSCC, 2013)