A Pipelined Distributed Arithmetic PFFT Processor. - Paul Chow; Zvonko G. Vranesic; Jui Lin Yen (IEEE Trans. Computers, 1983)

Architectural Tradeoffs in the Design of MIPS-X. - Paul Chow; Mark Horowitz (ISCA, 1987)

Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency. - Jonathan Rose; Robert J. Francis; David M. Lewis; Paul Chow (IEEE J. Solid State Circuits, 1990)

Generalized cascade Viterbi decoder-a locally connected multiprocessor with linear speed-up. - Gennady Feygin; Patrick Glenn Gulak; Paul Chow (ICASSP, 1991)

A streamlined DSP microprocessor architecture. - Michael Takefman; Paul Chow (ICASSP, 1991)

The effect of logic block architecture on FPGA performance. - Satwant Singh; Jonathan Rose; Paul Chow; David M. Lewis (IEEE J. Solid State Circuits, 1992)

Minimizing Error and VLSI Complexity in the Multiplication-Free Approximation of Arithmetic Coding. - Gennady Feygin; P. Glenn Gulak; Paul Chow (Data Compression Conference, 1993)

A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. - Gennady Feygin; Paul Chow; P. Glenn Gulak; John Chappel; Grant Goodes; Oswin Hall; Ahmad Sayes; Satwant Singh; Michael B. Smith; Steven J. E. Wilton (ISCAS, 1993)

A multiprocessor architecture for Viterbi decoders with linear speedup. - Gennady Feygin; Patrick Glenn Gulak; Paul Chow (IEEE Trans. Signal Process., 1993)

Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression. - Gennady Feygin; P. Glenn Gulak; Paul Chow (Data Compression Conference, 1994)

Application-driven design of DSP architectures and compilers. - Mazen A. R. Saghir; Paul Chow; Corinna G. Lee (ICASSP (2), 1994)

Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding. - Gennady Feygin; P. Glenn Gulak; Paul Chow (Inf. Process. Manag., 1994)

A Field-Programmable Mixed-Analog-Digital Array. - Paul Chow; P. Glenn Gulak (FPGA, 1995)

How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors? - Keith I. Farkas; Norman P. Jouppi; Paul Chow (HPCA, 1995)

Exploiting Dual Data-Memory Banks in Digital Signal Processors. - Mazen A. R. Saghir; Paul Chow; Corinna G. Lee (ASPLOS, 1996)

OneChip: an FPGA processor with reconfigurable logic. - Ralph Wittig; Paul Chow (FCCM, 1996)

RACER: a reconfigurable constraint-length 14 Viterbi decoder. - David Yeh; Gennady Feygin; Paul Chow (FCCM, 1996)

Register File Design Considerations in Dynamically Scheduled Processors. - Keith I. Farkas; Norman P. Jouppi; Paul Chow (HPCA, 1996)

Memory-System Design Considerations for Dynamically-Scheduled Processors. - Keith I. Farkas; Paul Chow; Norman P. Jouppi; Zvonko G. Vranesic (ISCA, 1997)

The Multicluster Architecture: Reducing Cycle Time Through Partitioning. - Keith I. Farkas; Paul Chow; Norman P. Jouppi; Zvonko G. Vranesic (MICRO, 1997)

The Transmogrifier-2: a 1 million gate rapid-prototyping system. - David M. Lewis; David R. Galloway; Marcus van Ierssel; Jonathan Rose; Paul Chow (IEEE Trans. Very Large Scale Integr. Syst., 1998)

DES Cracking on the Transmogrifier 2a. - Ivan Hamer; Paul Chow (CHES, 1999)

Memory Interfacing and Instruction Specification for Reconfigurable Processors. - Jeffrey A. Jacob; Paul Chow (FPGA, 1999)

The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning. - Keith I. Farkas; Paul Chow; Norman P. Jouppi; Zvonko G. Vranesic (Int. J. Parallel Program., 1999)

The design of an SRAM-based field-programmable gate array. I. Architecture. - Paul Chow; Soon Ong Seo; Jonathan Rose; Kevin Chung; Gerard Páez-Monzón; Immanuel Rahardja (IEEE Trans. Very Large Scale Integr. Syst., 1999)

The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout. - Paul Chow; Soon Ong Seo; Jonathan Rose; Kevin Chung; Gerard Páez-Monzón; Immanuel Rahardja (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Embedded ISA support for enhanced floating-point to fixed-point ANSI-C compilation. - Tor M. Aamodt; Paul Chow (CASES, 2000)

A Scheduler ASIC for a Programmable Packet Switch. - L. Louis Zhang; Brent Beacham; Massoud R. Hashemi; Paul Chow; Alberto Leon-Garcia (IEEE Micro, 2000)

The effect of reconfigurable units in superscalar processors. - Jorge E. Carrillo; Paul Chow (FPGA, 2001)

Standardizing the Performance Assessment of Reconfigurable Processor Architectures. - Lesley Shannon; Paul Chow (FCCM, 2003)

A framework for modeling and optimization of prescient instruction prefetch. - Tor M. Aamodt; Pedro Marcuello; Paul Chow; Antonio González 001; Per Hammarlund; Hong Wang 003; John Paul Shen (SIGMETRICS, 2003)

Reconfigurable Molecular Dynamics Simulator. - Navid Azizi; Ian Kuon; Aaron Egier; Ahmad Darabiha; Paul Chow (FCCM, 2004)

FPGA-based supercomputing: an implementation for molecular dynamics. - Ian Kuon; Navid Azizi; Ahmad Darabiha; Aaron Egier; Paul Chow (FPGA, 2004)

Using reconfigurability to achieve real-time profiling for hardware/software codesign. - Lesley Shannon; Paul Chow (FPGA, 2004)

Maximizing system performance: using reconfigurability to monitor system communications. - Lesley Shannon; Paul Chow (FPT, 2004)

Hardware Support for Prescient Instruction Prefetch. - Tor M. Aamodt; Paul Chow; Per Hammarlund; Hong Wang 003; John Paul Shen (HPCA, 2004)

Simplifying the Integration of Processing Elements in Computing Systems Using a Programmable Controller. - Lesley Shannon; Paul Chow (FCCM, 2005)

Leveraging Reconfigurability in the Design Process. - Lesley Shannon; Paul Chow (FPL, 2005)

Designing an FPGA SoC Using a Standardized IP Block Interface. - Lesley Shannon; Blair Fort; Samir Parikh; Arun Patel; Manuel Saldaña; Paul Chow (FPT, 2005)

A Scalable FPGA-based Multiprocessor. - Arun Patel; Christopher A. Madill; Manuel Saldaña; Chris Comis; Régis Pomès; Paul Chow (FCCM, 2006)

The routability of multiprocessor network topologies in FPGAs. - Manuel Saldaña; Lesley Shannon; Paul Chow (FPGA, 2006)

TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs. - Manuel Saldaña; Paul Chow (FPL, 2006)

A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification. - Lesley Shannon; Blair Fort; Samir Parikh; Arun Patel; Manuel Saldaña; Paul Chow (FPL, 2006)

Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPI. - Manuel Saldaña; Daniel Nunes; Emanuel Ramalho; Paul Chow (ReConFig, 2006)

A CMOS Image Sensor for DNA Microarrays. - Samir Parikh; P. Glenn Gulak; Paul Chow (CICC, 2007)

An FPGA Implementation of Reciprocal Sums for SPME. - Sam Lee; Paul Chow (ERSA, 2007)

Integrating FPGAs in high-performance computing: introduction. - Paul Chow; Mike Hutton (FPGA, 2007)

Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor. - Chichyang Chen; Paul Chow (ACM Great Lakes Symposium on VLSI, 2007)

Optimization of data prefetch helper threads with path-expression based statistical modeling. - Tor M. Aamodt; Paul Chow (ICS, 2007)

Routability of Network Topologies in FPGAs. - Manuel Saldaña; Lesley Shannon; Jia Shuo Yue; Sikang Bian; John Craig; Paul Chow (IEEE Trans. Very Large Scale Integr. Syst., 2007)

SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse. - Lesley Shannon; Paul Chow (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Investigation of Programming Models for Emerging FPGA-Based High Performance Computing Systems. - Andrew W. H. House; Paul Chow (FCCM, 2008)

FPGA acceleration of Monte-Carlo based credit derivative pricing. - Alexander Kaganov; Paul Chow; Asif Lakhany (FPL, 2008)

A profiler for a heterogeneous multi-core multi-FPGA system. - Daniel Nunes; Manuel Saldaña; Paul Chow (FPT, 2008)

A Message-Passing Hardware/Software Co-simulation Environment to Aid in Reconfigurable Computing Design Using TMD-MPI. - Manuel Saldaña; Emanuel Ramalho; Paul Chow (ReConFig, 2008)

MPI as an abstraction for software-hardware interaction for HPRCs. - Manuel Saldaña; Arun Patel; Christopher A. Madill; Daniel Nunes; Danyao Wang; Henry Styles; Andrew Putnam; Ralph Wittig; Paul Chow (HPRCTA@SC, 2008)

Compile-time and instruction-set methods for improving floating- to fixed-point conversion accuracy. - Tor M. Aamodt; Paul Chow (ACM Trans. Embed. Comput. Syst., 2008)

FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy. - Jason Luu; Keith Redmond; William Lo; Paul Chow; Lothar Lilge; Jonathan Rose (FCCM, 2009)

A high-performance FPGA architecture for restricted boltzmann machines. - Daniel Le Ly; Paul Chow (FPGA, 2009)

A multi-FPGA architecture for stochastic Restricted Boltzmann Machines. - Daniel Le Ly; Paul Chow (FPL, 2009)

The challenges of using an embedded MPI for hardware-based processing nodes. - Daniel Le Ly; Manuel Saldaña; Paul Chow (FPT, 2009)

Programming the Nallatech Xeon + multi-FPGA heterogeneous platform. - Paul Chow; Manuel Saldaña; Arun Patel; Christopher A. Madill (Hot Chips Symposium, 2009)

Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture. - Jiang Jiang; Vincent Mirian; Kam Pui Tang; Paul Chow; Zuocheng Xing (ReConFig, 2009)

A Message-Passing Hardware/Software Cosimulation Environment for Reconfigurable Computing Systems. - Manuel Saldaña; Emanuel Ramalho; Paul Chow (Int. J. Reconfigurable Comput., 2009)

Integrating High-Level Synthesis into MPI. - Andrew W. H. House; Manuel Saldaña; Paul Chow (FCCM, 2010)

Acceleration of an analytical approach to collateralized debt obligation pricing. - Dharmendra P. Gupta; Paul Chow (FPGA, 2010)

Using Partial Reconfiguration in an Embedded Message-Passing System. - Manuel Saldaña; Arun Patel; Hao Jun Liu; Paul Chow (ReConFig, 2010)

Virtualized Application Networking Infrastructure. - Hadi Bannazadeh; Alberto Leon-Garcia; Keith Redmond; Gordon Tam; Arbab Khan; Mingliang Ma; Saleh Dani; Paul Chow (TRIDENTCOM, 2010)

High-Performance Reconfigurable Hardware Architecture for Restricted Boltzmann Machines. - Daniel Le Ly; Paul Chow (IEEE Trans. Neural Networks, 2010)

MPI as a Programming Model for High-Performance Reconfigurable Computers. - Manuel Saldaña; Arun Patel; Christopher A. Madill; Daniel Nunes; Danyao Wang; Paul Chow; Ralph Wittig; Henry Styles; Andrew Putnam (ACM Trans. Reconfigurable Technol. Syst., 2010)

Building a multi-FPGA virtualized restricted boltzmann machine architecture using embedded MPI. - Charles Lo; Paul Chow (FPGA, 2011)

Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL Method. - Yuan Li; Paul Chow; Jiang Jiang; Minxuan Zhang (FPL, 2011)

Hardware Support for Broadcast and Reduce in MPSoC. - Yuanxi Peng; Manuel Saldaña; Paul Chow (FPL, 2011)

FPGA Acceleration of MultiFactor CDO Pricing. - Alexander Kaganov; Asif Lakhany; Paul Chow (ACM Trans. Reconfigurable Technol. Syst., 2011)

Leveraging reconfigurability in the hardware/software codesign process. - Lesley Shannon; Paul Chow (ACM Trans. Reconfigurable Technol. Syst., 2011)

OpenCL memory infrastructure for FPGAs (abstract only). - S. Alexander Chin; Paul Chow (FPGA, 2012)

FCache: a system for cache coherent processing on FPGAs. - Vincent Mirian; Paul Chow (FPGA, 2012)

K-means implementation on FPGA for high-dimensional data using triangle inequality. - Zhongduo Lin; Charles Lo; Paul Chow (FPL, 2012)

Software/hardware framework for generating parallel Gaussian random numbers based on the Monty Python method. - Yuan Li; Paul Chow; Jiang Jiang; Minxuan Zhang; Shaojun Wei (FPT, 2012)

A high-performance architecture for training Viola-Jones object detectors. - Charles Lo; Paul Chow (FPT, 2012)

Managing mutex variables in a cache-coherent shared-memory system for FPGAs. - Vincent Mirian; Paul Chow (FPT, 2012)

SimXMD: Integrated debugging of C code and hardware components. - Ruediger Willenberg; Paul Chow (FPT, 2012)

An implementation of a directory protocol for a cache coherent system on FPGAs. - Vincent Mirian; Paul Chow (ReConFig, 2012)

Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms. - Manuel Saldaña; Arun Patel; Hao Jun Liu; Paul Chow (Int. J. Reconfigurable Comput., 2012)

A remote memory access infrastructure for global address space programming models in FPGAs. - Ruediger Willenberg; Paul Chow (FPGA, 2013)

NetThreads-10G: Software packet processing on NetFPGA-10G in a virtualized networking environment demonstration abstract. - Stuart Byma; J. Gregory Steffan; Paul Chow (FPL, 2013)

Simulation-based HW/SW co-debugging for field-programmable systems-on-chip. - Ruediger Willenberg; Paul Chow (FPL, 2013)

SimXMD: Simulation-based HW/SW co-debugging. - Ruediger Willenberg; Paul Chow (FPL, 2013)

Why Put FPGAs in your CPU socket? - Paul Chow (FPT, 2013)

ZCluster: A Zynq-based Hadoop cluster. - Zhongduo Lin; Paul Chow (FPT, 2013)

FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStack. - Stuart Byma; J. Gregory Steffan; Hadi Bannazadeh; Alberto Leon-Garcia; Paul Chow (FCCM, 2014)

MPack: global memory optimization for stream applications in high-level synthesis. - Jasmina Vasiljevic; Paul Chow (FPGA, 2014)

Using an OpenCL framework to evaluate interconnect implementations on FPGAs. - Vincent Mirian; Paul Chow (FPL, 2014)

Using buffer-to-BRAM mapping approaches to trade-off throughput vs. memory use. - Jasmina Vasiljevic; Paul Chow (FPL, 2014)

An efficient FPGA implementation of QR decomposition using a novel systolic array architecture based on enhanced vectoring CORDIC. - Jianfeng Zhang; Paul Chow; Hengzhu Liu (FPT, 2014)

A Heterogeneous GASNet Implementation for FPGA-accelerated Computing. - Ruediger Willenberg; Paul Chow (PGAS, 2014)

Virtualized Reconfigurable Hardware Resources in the SAVI Testbed. - Stuart Byma; Hadi Bannazadeh; Alberto Leon-Garcia; J. Gregory Steffan; Paul Chow (TRIDENTCOM, 2014)

A Software Parallel Programming Approach to FPGA-Accelerated Computing. - Ruediger Willenberg; Paul Chow (CoRR, 2014)

Benefits of Adding Hardware Support for Broadcast and Reduce Operations in MPSoC Applications. - Yuanxi Peng; Manuel Saldaña; Christopher A. Madill; Xiaofeng Zou; Paul Chow (ACM Trans. Reconfigurable Technol. Syst., 2014)

Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method. - Yuan Li; Paul Chow; Jiang Jiang; Minxuan Zhang; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Expanding OpenFlow Capabilities with Virtualized Reconfigurable Hardware. - Stuart Byma; Naif Tarafdar; Talia Xu; Hadi Bannazadeh; Alberto Leon-Garcia; Paul Chow (FPGA, 2015)

Exploring pipe implementations using an OpenCL framework for FPGAs. - Vincent Mirian; Paul Chow (FPT, 2015)

OpenCL library of stream memory components targeting FPGAs. - Jasmina Vasiljevic; Ralph Wittig; Paul Schumacher; Jeff Fifield; Fernando Martinez-Vallina; Henry Styles; Paul Chow (FPT, 2015)

FPGA implementation of low-power and high-PSNR DCT/IDCT architecture based on adaptive recoding CORDIC. - Jianfeng Zhang; Paul Chow; Hengzhu Liu (FPT, 2015)

Architecture Exploration for Data Intensive Applications. - Fernando Martin del Campo; Paul Chow (MEMSYS, 2015)

Evaluating shared virtual memory in an OpenCL framework for embedded systems on FPGAs. - Vincent Mirian; Paul Chow (ReConFig, 2015)

UT-OCL: an OpenCL framework for embedded systems using xilinx FPGAs. - Vincent Mirian; Paul Chow (ReConFig, 2015)

An Enhanced Adaptive Recoding Rotation CORDIC. - Jianfeng Zhang; Paul Chow; Hengzhu Liu (ACM Trans. Reconfigurable Technol. Syst., 2015)

Accelerating Apache Spark Big Data Analysis with FPGAs. - Ehsan Ghasemi; Paul Chow (FCCM, 2016)

A Scalable Heterogeneous Dataflow Architecture For Big Data Analytics Using FPGAs (Abstract Only). - Ehsan Ghasemi; Paul Chow (FPGA, 2016)

Model-based optimization of High Level Synthesis directives. - Charles Lo; Paul Chow (FPL, 2016)

Caffeinated FPGAs: FPGA framework For Convolutional Neural Networks. - Roberto DiCecco; Griffin Lacey; Jasmina Vasiljevic; Paul Chow; Graham W. Taylor; Shawki Areibi (FPT, 2016)

Extracting Designs of Secure IPs Using FPGA CAD Tools. - Vincent Mirian; Paul Chow (ACM Great Lakes Symposium on VLSI, 2016)

CORDIC-Based Enhanced Systolic Array Architecture for QR Decomposition. - Jianfeng Zhang; Paul Chow; Hengzhu Liu (ACM Trans. Reconfigurable Technol. Syst., 2016)

Enabling network function virtualization over heterogeneous resources. - Thomas Lin; Naif Tarafdar; Byungchul Park; Paul Chow; Alberto Leon-Garcia (APNOMS, 2017)

Building the Reconfigurable Cloud Ecosystem. - Paul Chow (ETCD@ASPLOS, 2017)

Packet Matching on FPGAs Using HMC Memory: Towards One Million Rules. - Daniel Rozhko; Geoffrey Elliott; Daniel Ly-Ma; Paul Chow; Hans-Arno Jacobsen (FPGA, 2017)

Enabling Flexible Network FPGA Clusters in a Heterogeneous Cloud Data Center. - Naif Tarafdar; Thomas Lin; Eric Fukuda; Hadi Bannazadeh; Alberto Leon-Garcia; Paul Chow (FPGA, 2017)

Heterogeneous virtualized network function framework for the data center. - Naif Tarafdar; Thomas Lin; Nariman Eskandari; David Lion; Alberto Leon-Garcia; Paul Chow (FPL, 2017)

FPGA-based training of convolutional neural networks with a reduced precision floating-point library. - Roberto DiCecco; Lin Sun; Paul Chow (FPT, 2017)

An FPGA-based processor for training convolutional neural networks. - Zhiqiang Liu; Yong Dou; Jingfei Jiang; Qiang Wang 006; Paul Chow (FPT, 2017)

Enabling FPGAs as a True Device in the OpenCL Standard: Bridging the Gap for FPGAs. - Vincent Mirian; Paul Chow (IWOCL, 2017)

Task replication and control for highly parallel in-memory stores. - Fernando Martin del Campo; Paul Chow (MEMSYS, 2017)

Build fast, trade fast: FPGA-based high-frequency trading using high-level synthesis. - Andrew Boutros; Brett Grady; Mustafa Abbas; Paul Chow (ReConFig, 2017)

A High-Level Synthesis Case Study on Light Propagation Simulation in Turbid Media. - Abdul-Amir Yassine; Yasmin Afsharnejad; Omar Ragheb; Vaughn Betz; Paul Chow (FCCM, 2018)

Multi-fidelity Optimization for High-Level Synthesis Directives. - Charles Lo; Paul Chow (FPL, 2018)

HLS-based FPGA Acceleration of Light Propagation Simulation in Turbid Media. - Yasmin Afsharnejad; Abdul-Amir Yassine; Omar Ragheb; Paul Chow; Vaughn Betz (HEART, 2018)

Designing for FPGAs in the Cloud. - Naif Tarafdar; Nariman Eskandari; Thomas Lin; Paul Chow (IEEE Des. Test, 2018)

Galapagos: A Full Stack Approach to FPGA Integration in the Cloud. - Naif Tarafdar; Nariman Eskandari; Varun Sharma; Charles Lo; Paul Chow (IEEE Micro, 2018)

Sonar: Writing Testbenches through Python. - Varun Sharma; Naif Tarafdar; Paul Chow (FCCM, 2019)

A Modular Heterogeneous Stack for Deploying FPGAs and CPUs in the Data Center. - Nariman Eskandari; Naif Tarafdar; Daniel Ly-Ma; Paul Chow (FPGA, 2019)

The Network Management Unit (NMU): Securing Network Access for Direct-Connected FPGAs. - Daniel Rozhko; Paul Chow (FPGA, 2019)

Introducing ReCPRI: A Field Re-configurable Protocol for Backhaul Communication in a Radio Access Network. - Juan Camilo Vega; Qianfeng Shen; Alberto Leon-Garcia; Paul Chow (IM, 2019)

Accelerating Apache Spark with FPGAs. - Ehsan Ghasemi; Paul Chow (Concurr. Comput. Pract. Exp., 2019)

Hierarchical Modelling of Generators in Design-Space Exploration. - Charles Lo; Paul Chow (FCCM, 2020)

AIgean: An Open Framework for Machine Learning on Heterogeneous Clusters. - Naif Tarafdar; Giuseppe Di Guglielmo; Philip C. Harris; Jeffrey D. Krupa; Vladimir Loncar; Dylan S. Rankin; Nhan Tran; Zhenbin Wu; Qianfeng Shen; Paul Chow (FCCM, 2020)

FFShark: A 100G FPGA Implementation of BPF Filtering for Wireshark. - Juan Camilo Vega; Marco Antonio Merlini; Paul Chow (FCCM, 2020)

SHIP: Storage for Hybrid Interconnected Processors. - Juan Camilo Vega; Qianfeng Clark Shen; Paul Chow (FCCM, 2020)

Pharos: a Performance Monitor for Multi-FPGA Systems. - Arzhang Rafii; Paul Chow; Welson Sun (FCCM, 2021)

FFIVE: An FPGA Framework for Interactive VNF Environments. - Juan Camilo Vega; Mohammad Ewais; Alberto Leon-Garcia; Paul Chow (FCCM, 2021)

Interactive Debugging at IP Block Interfaces in FPGAs. - Marco Antonio Merlini; Isamu Poy; Paul Chow (FPGA, 2021)

Exploring PGAS Communication for Heterogeneous Clusters with FPGAs. - Varun Sharma; Paul Chow (FPGA, 2021)

RIFL: A Reliable Link Layer Network Protocol for FPGA-to-FPGA Communication. - Qianfeng Clark Shen; Jun Zheng; Paul Chow (FPGA, 2021)

Pharos: a Multi-FPGA Performance Monitor. - Arzhang Rafii; Welson Sun; Paul Chow (FPL, 2021)

A Framework Integrating FPGAs in VNF Networks. - Mohammad Ewais; Juan Camilo Vega; Alberto Leon-Garcia; Paul Chow (NoF, 2021)

A PGAS Communication Library for Heterogeneous Clusters. - Varun Sharma; Paul Chow (CoRR, 2021)

FPGA Implementation of an Improved OMP for Compressive Sensing Reconstruction. - Jun Li 094; Paul Chow; Yuanxi Peng; Tian Jiang (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Parallel CRC On An FPGA At Terabit Speeds. - Qianfeng Clark Shen; Juan Camilo Vega; Paul Chow (FPT, 2022)

RIFL: a reliable link layer network protocol for data center communication. - Qianfeng Shen; Jun Zheng; Paul Chow (JOCN, 2022)

The Future of FPGA Acceleration in Datacenters and the Cloud. - Christophe Bobda; Joel Mandebi Mbongue; Paul Chow; Mohammad Ewais; Naif Tarafdar; Juan Camilo Vega; Ken Eguro; Dirk Koch; Suranga Handagala; Miriam Leeser; Martin C. Herbordt; Hafsah Shahzad; et al. (ACM Trans. Reconfigurable Technol. Syst., 2022)

AIgean: An Open Framework for Deploying Machine Learning on Heterogeneous Clusters. - Naif Tarafdar; Giuseppe Di Guglielmo; Philip C. Harris; Jeffrey D. Krupa; Vladimir Loncar; Dylan S. Rankin; Nhan Tran; Zhenbin Wu; Qianfeng Shen; Paul Chow (ACM Trans. Reconfigurable Technol. Syst., 2022)

A Lightweight Routing Layer Using a Reliable Link-Layer Protocol. - Qiangfeng Shen; Paul Chow (CloudCom, 2023)

Partitioning Large-Scale, Multi-FPGA Applications for the Data Center. - Mohammadmahdi Mazraeli; Yu Gao; Paul Chow (FPL, 2023)

Disaggregated Memory in the Datacenter: A Survey. - Mohammad Ewais; Paul Chow (IEEE Access, 2023)

A Lightweight Routing Layer Using a Reliable Link-Layer Protocol. - Qianfeng Shen; Paul Chow (CoRR, 2023)

DDC: A Vision for a Disaggregated Datacenter. - Mohammad Ewais; Paul Chow (CoRR, 2024)

The Feasibility of Implementing Large-Scale Transformers on Multi-FPGA Platforms. - Yu Gao; Juan Camilo Vega; Paul Chow (CoRR, 2024)

The Software-Centric Approach of SYNERGY: Technical Perspective. - Paul Chow (Commun. ACM, 2024)

Derek Chiou. - Doug Burger; Paul Chow; Joel S. Emer; Mark D. Hill; James C. Hoe; Masato Motomura (IEEE Micro, 2025)