Silicides and local interconnections for high-performance VLSI applications. - Randy W. Mann; Larry A. Clevenger; Paul D. Agnello; Francis R. White (IBM J. Res. Dev., 1995)

Process requirements for continued scaling of CMOS-the need and prospects for atomic-level manipulation. - Paul D. Agnello (IBM J. Res. Dev., 2002)

Optimization of silicon technology for the IBM System z9. - Daniel J. Poindexter; Scott R. Stiffler; Philip T. Wu; Paul D. Agnello; Thomas Ivers; Shreesh Narasimha; Thomas B. Faure; Jed H. Rankin; David A. Grosch; Marc D. Knox; Daniel C. Edelstein; Mukesh Khare; et al. (IBM J. Res. Dev., 2007)

45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications. - Subramanian S. Iyer; Greg G. Freeman; Colin Brodsky; Anthony I. Chou; Dan Corliss; Sameer H. Jain; Naftali E. Lustig; Vincent McGahay; Shreesh Narasimha; James P. Norum; Karen A. Nummy; Paul C. Parries; et al. (IBM J. Res. Dev., 2011)

Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond. - Balaji Jayaraman; Sneha Gupta; Yanli Zhang; Puneet Goyal; Herbert Ho; Rishikesh Krishnan; Sunfei Fang; Sungjae Lee; Douglas Daley; Kevin McStay; Bernhard Wunder; John Barth 001; et al. (ICICDT, 2012)

Performance-optimized gate-first 22-nm SOI technology with embedded DRAM. - Gregory Freeman; Paul Chang; E. R. Engbrecht; K. J. Giewont; David F. Hilscher; M. Lagus; Timothy J. McArdle; B. Morgenfeld; Shreesh Narasimha; James P. Norum; K. A. Nummy; Paul C. Parries; et al. (IBM J. Res. Dev., 2015)