Synthetic circuit generation using clustering and iteration. - Paul D. Kundarewich; Jonathan Rose (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Architecture-specific packing for virtex-5 FPGAs. - Taneem Ahmed; Paul D. Kundarewich; Jason Helge Anderson; Brad L. Taylor; Rajat Aggarwal (FPGA, 2008)

Packing Techniques for Virtex-5 FPGAs. - Taneem Ahmed; Paul D. Kundarewich; Jason Helge Anderson (ACM Trans. Reconfigurable Technol. Syst., 2009)