An integrated automatic design system for complex DSP algorithms. - Jef L. van Meerbergen; Jos Huisken; Paul E. R. Lippens; O. McArdle; R. Segers; Gert Goossens; Jan Vanhoof; Dirk Lanneer; Francky Catthoor; Hugo De Man (J. VLSI Signal Process., 1990)

PHIDEO: a silicon compiler for high speed algorithms. - Paul E. R. Lippens; Jef L. van Meerbergen; Albert van der Werf; Wim F. J. Verhaegh; B. T. McSweeney; Jos Huisken; O. McArdle (EURO-DAC, 1991)

Improved force-directed scheduling. - Wim F. J. Verhaegh; Emile H. L. Aarts; Jan H. M. Korst; Paul E. R. Lippens (EURO-DAC, 1991)

Hierarchical Retiming Including Pipelining. - Albert van der Werf; B. T. McSweeney; Jef L. van Meerbergen; Paul E. R. Lippens; Wim F. J. Verhaegh (VLSI, 1991)

Efficiency improvements for force-directed scheduling. - Wim F. J. Verhaegh; Paul E. R. Lippens; Emile H. L. Aarts; Jan H. M. Korst; Albert van der Werf; Jef L. van Meerbergen (ICCAD, 1992)

Area optimization of multi-functional processing units. - Albert van der Werf; M. J. H. Peek; Emile H. L. Aarts; Jef L. van Meerbergen; Paul E. R. Lippens; Wim F. J. Verhaegh (ICCAD, 1992)

Allocation of multiport memories for hierarchical data stream. - Paul E. R. Lippens; Jef L. van Meerbergen; Wim F. J. Verhaegh; Albert van der Werf (ICCAD, 1993)

A new method for retiming multi-functional processing units. - Albert van der Werf; Emile H. L. Aarts; E. W. Heijnen; Jef L. van Meerbergen; Wim F. J. Verhaegh; Paul E. R. Lippens (VLSI, 1993)

Architectural strategies for high-throughput applications. - Jef L. van Meerbergen; Paul E. R. Lippens; B. T. McSweeney; Wim F. J. Verhaegh; Albert van der Werf; A. van Zanten (J. VLSI Signal Process., 1993)

Optimization of Address Generator Hardware. - Douglas M. Grant; Jef L. van Meerbergen; Paul E. R. Lippens (EDAC-ETC-EUROASIC, 1994)

Efficient timing constraint derivation for optimal retiming high speed processing units. - Albert van der Werf; Jef L. van Meerbergen; Emile H. L. Aarts; Wim F. J. Verhaegh; Paul E. R. Lippens (HLSS, 1994)

CAD challenges in multimedia computing. - Paul E. R. Lippens; Vijay Nagasamy; Wayne H. Wolf (ICCAD, 1995)

Improved force-directed scheduling in high-throughput digital signal processing. - Wim F. J. Verhaegh; Paul E. R. Lippens; Emile H. L. Aarts; Jan H. M. Korst; Jef L. van Meerbergen; Albert van der Werf (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

PHIDEO: High-level synthesis for high throughput applications. - Jef L. van Meerbergen; Paul E. R. Lippens; Wim F. J. Verhaegh; Albert van der Werf (J. VLSI Signal Process., 1995)

Multidimensional Periodic Scheduling Model and Complexity. - Wim F. J. Verhaegh; Paul E. R. Lippens; Emile H. L. Aarts; Jef L. van Meerbergen; Albert van der Werf (Euro-Par, Vol. II, 1996)

A video signal processor for motion-compensated field-rate upconversion in consumer television. - Paul E. R. Lippens; Bart De Loore; G. de Haan; P. Eeckhout; H. Huijgen; A. Loning; B. T. McSweeney; M. Verstraeien; B. Pahn; J. Kettenis (IEEE J. Solid State Circuits, 1996)

Multidimensional periodic scheduling: a solution approach. - Wim F. J. Verhaegh; Paul E. R. Lippens; Emile H. L. Aarts; Jef L. van Meerbergen (ED&TC, 1997)

The Complexity of Multidimensional Periodic Scheduling. - Wim F. J. Verhaegh; Paul E. R. Lippens; Emile H. L. Aarts; Jef L. van Meerbergen; Albert van der Werf (Discret. Appl. Math., 1998)

Mapping Array Communication onto FIFO Communication - Towards an Implementation. - Jeffrey Kang; Albert van der Werf; Paul E. R. Lippens (ISSS, 2000)

HW-SW Co-Design and Verification of a Multi-Standard Video and Image Codec. - Rafael Peset Llopis; Marcel Oosterhuis; Ramanathan Sethuraman; Paul E. R. Lippens; Albert van der Werf; Steffen Maul; Jim Lin (ISQED, 2001)

A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems. - Om Prakash Gangwal; André Nieuwland; Paul E. R. Lippens (ISSS, 2001)

A two-stage solution approach to multidimensional periodicscheduling. - Wim F. J. Verhaegh; Emile H. L. Aarts; Paul C. N. van Gorp; Paul E. R. Lippens (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Correction to "a two-stage solution approach to multidimensional periodic scheduling". - Wim F. J. Verhaegh; Emile H. L. Aarts; Paul C. N. van Gorp; Paul E. R. Lippens (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems. - André Nieuwland; Jeffrey Kang; Om Prakash Gangwal; Ramanathan Sethuraman; Natalino G. Busá; Kees Goossens; Rafael Peset Llopis; Paul E. R. Lippens (Des. Autom. Embed. Syst., 2002)