A circuit level hot-carrier evaluation system. - Paul G. Y. Tsui; Peter M. Lee; Frank K. Baker; James D. Hayden; Lee Howington; Tom Tiwald; Brian Mowry (IEEE J. Solid State Circuits, 1991)

Study of BiCMOS logic gate configurations for improved low-voltage performance. - Paul G. Y. Tsui; Bernie Pappert; Shih-Wei Sun; John R. Yeargain (IEEE J. Solid State Circuits, 1993)

Limitation of CMOS supply-voltage scaling by MOSFET threshold-voltage variation. - Shih-Wei Sun; Paul G. Y. Tsui (IEEE J. Solid State Circuits, 1995)