A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology. - Zhongkai Wang; Minsoo Choi 002; Paul Kwon; Kyoungtae Lee; Bozhi Yin; Zhaokai Liu; Kwanseo Park; Ayan Biswas; Jaeduk Han; Sijun Du; Elad Alon (VLSI Technology and Circuits, 2022)

Accurate Statistical BER Analysis of DFE Error Propagation in the Presence of Residual ISI. - Kunmo Kim; Paul Kwon; Elad Alon (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS. - Zhongkai Wang; Minsoo Choi 002; Paul Kwon; Zhaokai Liu; Bozhi Yin; Kyoungtae Lee; Kwanseo Park; Ayan Biswas; Jaeduk Han; Sijun Du; Elad Alon (ISCAS, 2024)

BAG3++: An Extensible Generator Framework for Automated Layout-Aware AMS Design. - Felicia Guo; Bob L. Zhou; Ayan Biswas; Paul Kwon; Zhaokai Liu; Ken Ho; Vladimir Stojanovic; Borivoje Nikolic (IEEE Open J. Circuits Syst., 2025)