Digital pulse frequency demodulation using state-space filtering. - Paul Loewenstein (ICASSP, 1982)

Architecture and instruction set of a programmable LSI digital filter. - S. N. Terepin; Paul Loewenstein (ICASSP, 1983)

Closing the semantic gap. - Paul Loewenstein; Andrew Fox (Microprocess. Microprogramming, 1988)

Formal verification of state-machines using higher-order logic. - Paul Loewenstein (ICCD, 1989)

Reasoning about State Machines in Higher-Order Logic. - Paul Loewenstein (Hardware Specification, Verification and Synthesis, 1989)

Verification of a Multiprocessor Cache Protocol Using Simulation Relations and Higher-Order Logic. - Paul Loewenstein; David L. Dill (CAV, 1990)

Formal verification of cache systems using refinement relations. - Paul Loewenstein; David L. Dill (ICCD, 1990)

Learning to use HOL. - Paul Loewenstein (TPHOLs, 1991)

Verification of a Multiprocessor Cache Protocol Using Simulation Relations and Higher-Order Logic. - Paul Loewenstein (Formal Methods Syst. Des., 1992)

A Formal Theory of Simulations between Infinite Automata. - Paul Loewenstein (Formal Methods Syst. Des., 1993)

System Design Methodology of UltraSPARC-I. - Lawrence Yang; David Gao 001; Jamshid Mostoufi; Raju Joshi; Paul Loewenstein (DAC, 1995)

Formal Verification of Counterflow Pipeline Architecture. - Paul Loewenstein (TPHOLs, 1995)

The Oracle Sparc T5 16-Core Processor Scales to Eight Sockets. - John R. Feehrer; Sumti Jairath; Paul Loewenstein; Ram Sivaramakrishnan; David Smentek; Sebastian Turullols; Ali Vahidsafa (IEEE Micro, 2013)

4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor. - Penny Li; Jinuk Luke Shin; Georgios K. Konstadinidis; Francis Schumacher; Venkatram Krishnaswamy; Hoyeol Cho; Sudesna Dash; Robert P. Masleid; Chaoyang Zheng; Yuanjung David Lin; Paul Loewenstein; Heechoul Park; et al. (ISSCC, 2015)

M7: Oracle's Next-Generation Sparc Processor. - Kathirgamar Aingaran; Sumti Jairath; Georgios K. Konstadinidis; Serena Leung; Paul Loewenstein; Curtis McAllister; Stephen Phillips; Zoran Radovic; Ram Sivaramakrishnan; David Smentek; Thomas Wicki (IEEE Micro, 2015)

SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor. - Georgios K. Konstadinidis; Hongping Penny Li; Francis Schumacher; Venkatram Krishnaswamy; Hoyeol Cho; Sudesna Dash; Robert P. Masleid; Chaoyang Zheng; Yuanjung David Lin; Paul Loewenstein; Heechoul Park; Vijay Srinivasan; et al. (IEEE J. Solid State Circuits, 2016)

OmniXtend: Direct to Caches Over Commodity Fabric. - Marjan Radi; Wesley W. Terpstra; Paul Loewenstein; Dejan Vucinic (Hot Interconnects, 2019)