Power constrained test scheduling using power profile manipulation. - Paul M. Rosinger; Bashir M. Al-Hashimi; Nicola Nicolici (ISCAS (5), 2001)

Scan Architecture for Shift and Capture Cycle Power Reduction. - Paul M. Rosinger; Bashir M. Al-Hashimi; Nicola Nicolici (DFT, 2002)

Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding. - Paul M. Rosinger; Bashir M. Al-Hashimi; Nicola Nicolici (ICCD, 2002)

Power profile manipulation: a new approach for reducing test application time under power constraints. - Paul M. Rosinger; Bashir M. Al-Hashimi; Nicola Nicolici (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique. - Matheos Lampropoulos; Bashir M. Al-Hashimi; Paul M. Rosinger (DATE, 2004)

Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction. - Paul M. Rosinger; Bashir M. Al-Hashimi; Nicola Nicolici (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Rapid Generation of Thermal-Safe Test Schedules. - Paul M. Rosinger; Bashir M. Al-Hashimi; Krishnendu Chakrabarty (DATE, 2005)

Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling. - Enkelejda Tafaj; Paul M. Rosinger; Bashir M. Al-Hashimi; Krishnendu Chakrabarty (DFT, 2005)

Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy. - Alireza Ejlali; Marcus T. Schmitz; Bashir M. Al-Hashimi; Seyed Ghassem Miremadi; Paul M. Rosinger (ISLPED, 2005)

Minimizing test power in SRAM through reduction of pre-charge activity. - Luigi Dilillo; Paul M. Rosinger; Bashir M. Al-Hashimi; Patrick Girard 001 (DATE, 2006)

Reducing Power Dissipation in SRAM during Test. - Luigi Dilillo; Paul M. Rosinger; Bashir M. Al-Hashimi; Patrick Girard 001 (J. Low Power Electron., 2006)

Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits. - Paul M. Rosinger; Bashir M. Al-Hashimi; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems. - Alireza Ejlali; Bashir M. Al-Hashimi; Marcus T. Schmitz; Paul M. Rosinger; Seyed Ghassem Miremadi (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Resistive Bridging Faults DFT with Adaptive Power Management Awareness. - Urban Ingelsson; Paul M. Rosinger; S. Saqib Khursheed; Bashir M. Al-Hashimi; Peter Harrod (ATS, 2007)

Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks. - Alireza Ejlali; Bashir M. Al-Hashimi; Paul M. Rosinger; Seyed Ghassem Miremadi (DATE, 2007)

MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC. - Rishad A. Shafik; Paul M. Rosinger; Bashir M. Al-Hashimi (DDECS, 2008)

Bridge Defect Diagnosis for Multiple-Voltage Design. - S. Saqib Khursheed; Paul M. Rosinger; Bashir M. Al-Hashimi; Sudhakar M. Reddy; Peter Harrod (ETS, 2008)

SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation. - Rishad A. Shafik; Paul M. Rosinger; Bashir M. Al-Hashimi (IOLTS, 2008)

Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving. - Zhiyuan He 002; Zebo Peng; Petru Eles; Paul M. Rosinger; Bashir M. Al-Hashimi (J. Electron. Test., 2008)

Bridging Fault Test Method With Adaptive Power Management Awareness. - S. Saqib Khursheed; Urban Ingelsson; Paul M. Rosinger; Bashir M. Al-Hashimi; Peter Harrod (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks. - Alireza Ejlali; Bashir M. Al-Hashimi; Paul M. Rosinger; Seyed Ghassem Miremadi; Luca Benini (IEEE Trans. Very Large Scale Integr. Syst., 2010)